Abstract: A circuit including a power amplifier having a control terminal configured to control an output level of the power amplifier, a bias circuit in communication with the control terminal, the bias circuit including a tunable plurality of diodes in series configured to supply a bias voltage to the control terminal, and a control circuit in communication with the bias circuit configured to tune the plurality of diodes in series to create the bias voltage in response to a supply voltage of the amplifier.

Abstract: An outphasing amplifier includes a first class-E power amplifier having an output coupled to a first conductor and an input receiving a first RF drive signal. A first reactive element is coupled between the first conductor and a second conductor. A second reactive element is coupled between the second conductor and a third conductor. A second class-E power amplifier includes an output coupled to a fourth conductor and an input coupled to a second RF drive signal, a third reactive element coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load. An efficiency enhancement circuit is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits are coupled to the first and fourth conductors, respectively.

Abstract: The present disclosure includes dynamic power divider circuits and methods. In one embodiment, a dynamic power divider includes first and second quarter wave lines that receive an input signal and produce first and second signal on second terminals of the lines. Dynamic power division of the input signal uses a variable impedance circuit between the second terminal of the first quarter wave line and the second terminal of the second quarter wave line. The variable impedance may reduce impedance between two output paths as the input signal power increases or increase impedance between the output paths as the input signal power decreases.

Abstract: An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S1(t)). A first reactive element (CA-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (LA-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S2(t)), a third reactive element (CA-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (LEEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

Abstract: For generating quantized signals, a quantized phase domain related to quantized phases of an input signal is generated. Vectors that the input signal may occupy are calculated based on the quantized phase domain. A first quantized phase of a first component of the input signal is generated per the quantized phase domain, and a second quantized phase of a second component of the input signal is generated per the quantized phase domain.

Abstract: A circuit including a power amplifier having a control terminal configured to control an output level of the power amplifier, a bias circuit in communication with the control terminal, the bias circuit including a tunable plurality of diodes in series configured to supply a bias voltage to the control terminal, and a control circuit in communication with the bias circuit configured to tune the plurality of diodes in series to create the bias voltage in response to a supply voltage of the amplifier.

Abstract: Various aspects described herein relate to providing analog interference cancellation using digitally computed coefficients. An aggressor signal can be obtained from a transmitter chain of a radio frequency (RF) front end. A digital representation of the aggressor signal can be generated, and cancellation coefficients can be estimated for the digital representation of the aggressor signal. An analog cancellation signal can be generated based at least in part the cancellation coefficients and the digital representation of the aggressor signal. The analog cancellation signal can be added to a victim signal in a receiver chain of the RF front end to cancel interference to the victim signal from the aggressor signal.

Abstract: Aspects of the disclosure are directed to interference cancellation. A method of performing interference cancellation in a wireless device having a transmitter and a receiver includes enabling a radio frequency (RF) receive filter for a victim band from a plurality of RF receive filters in a receive path; measuring an RF filter characteristic of the enabled RF receive filter with an auxiliary receiver; configuring a programmable digital filter to match a filter characteristic to the measured RF filter characteristic to yield a reference signal; and providing the reference signal to the receive path for interference cancellation; and, the reference signal is subtracted from a receive signal in the receive path.

Abstract: An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S1(t)). A first reactive element (CA-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (LA-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S2(t)), a third reactive element (CA-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (LEEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

Abstract: The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main amplifier stage and peaking amplifier stage of a power amplifier receive a modulated supply voltage. The peaking amplifier stage is biased dynamically to adjust the bias of peaking stage to compensate for changes in the power supply voltage. A bias voltage may be increased as the supply voltage on the peaking stage decreases, and the bias voltage may be decreased as the supply voltage on the peaking stage increases. Accordingly, bias characteristics of the peaking stage are maintained across supply voltage variations, and the efficiency of the power amplifier is improved.

Abstract: An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S1(t)). A first reactive element (CA-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (LA-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S2(t)), a third reactive element (CA-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (LEEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

Abstract: Exemplary embodiments are related to a tri-phase digital polar modulator. A device may include a modulator configured to generate a primary phase modulated signal including the most significant bits (MSBs) of a modulated signal, a leading phase modulated signal including a first least significant bits (LSB) of the modulated signal, and a lagging phase modulated signal including a second LSB of the modulated signal. The device may also include a combination unit configured to add the primary phase modulated signal, the leading phase modulated signal, and the lagging phase modulated signal.

Abstract: The present disclosure includes dynamic power divider circuits and methods. In one embodiment, a dynamic power divider includes first and second quarter wave lines that receive an input signal and produce first and second signal on second terminals of the lines. Dynamic power division of the input signal uses a variable impedance circuit between the second terminal of the first quarter wave line and the second terminal of the second quarter wave line. The variable impedance may reduce impedance between two output paths as the input signal power increases or increase impedance between the output paths as the input signal power decreases.

Abstract: Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.

Abstract: The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main and peaking amplifier receive dynamic power supply voltages to operate an RF power amplifier in a high efficiency range for a particular output voltage. The power supply voltages may be changed based on an output voltage so that the power amplifier operates within a high efficiency plateau. In one embodiment, different discrete power supply voltage levels are used for different output voltage ranges. In another embodiment, a continuous time varying power supply voltage is provided as the power supply voltage. A dynamic supply voltage may be generated having a lower frequency than a signal path of the power amplifier.

Abstract: An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S1(t)). A first reactive element (CA-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (LA-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S2(t)), a third reactive element (CA-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (LEEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

Abstract: A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input signal is generated. The first signal has quantized levels representing the input signal. A pulse width modulated (PWM) sequence that is representative of the first signal is generated. A second signal that is the PWM sequence mixed with a carrier signal is generated. An error signal is generated in response to the first signal and modeled from the second signal. The error signal is added to the input signal.

Abstract: The present disclosure includes circuits and methods for power amplifiers. In one embodiment, a main amplifier stage and peaking amplifier stage of a power amplifier receive a modulated supply voltage. The peaking amplifier stage is biased dynamically to adjust the bias of peaking stage to compensate for changes in the power supply voltage. A bias voltage may be increased as the supply voltage on the peaking stage decreases, and the bias voltage may be decreased as the supply voltage on the peaking stage increases. Accordingly, bias characteristics of the peaking stage are maintained across supply voltage variations, and the efficiency of the power amplifier is improved.

Abstract: Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.

Abstract: Exemplary embodiments are related to a tri-phase digital polar modulator. A device may include a modulator configured to generate a primary phase modulated signal including the most significant bits (MSBs) of a modulated signal, a leading phase modulated signal including a first least significant bits (LSB) of the modulated signal, and a lagging phase modulated signal including a second LSB of the modulated signal.