Patents by Inventor Joonkyu Rhee

Joonkyu Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573651
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Joonkyu Rhee, Ji-Hye Lee, Chanmi Lee, Taeseop Choi
  • Publication number: 20190287975
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun KIM, Joonkyu RHEE, Ji-Hye Lee, Chanmi LEE, Taeseop CHOI
  • Patent number: 10396083
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Joonkyu Rhee, Ji-Hye Lee, Chanmi Lee, Taeseop Choi
  • Patent number: 10153283
    Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Chanmi Lee, Joonkyu Rhee, Ji-Hye Lee, Taeseop Choi
  • Publication number: 20180261601
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Application
    Filed: May 9, 2018
    Publication date: September 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun KIM, Joonkyu Rhee, Ji-Hye Lee, Chanmi Lee, Taeseop Choi
  • Patent number: 9997521
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Joonkyu Rhee, Ji-Hye Lee, Chanmi Lee, Taeseop Choi
  • Publication number: 20170294439
    Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.
    Type: Application
    Filed: February 15, 2017
    Publication date: October 12, 2017
    Inventors: Nam-Gun KIM, Chanmi Lee, Joonkyu Rhee, Ji-Hye Lee, Taeseop Choi
  • Publication number: 20170271340
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Application
    Filed: January 13, 2017
    Publication date: September 21, 2017
    Inventors: Nam-Gun KIM, Joonkyu RHEE, Ji-Hye LEE, Chanmi LEE, Taeseop CHOI
  • Patent number: 9142757
    Abstract: A magnetic memory device may include a lower electrode on a substrate, a memory element on the lower electrode, an upper electrode on the memory element, and a protection spacer enclosing a portion of a side surface of the lower electrode and protruding laterally from the side surface of the lower electrode. The protection spacer may have a bottom surface that is positioned at a level higher than that of a bottom surface of the lower electrode.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Hyungjoon Kwon, Joonkyu Rhee
  • Publication number: 20150194595
    Abstract: A magnetic memory device may include a lower electrode on a substrate, a memory element on the lower electrode, an upper electrode on the memory element, and a protection spacer enclosing a portion of a side surface of the lower electrode and protruding laterally from the side surface of the lower electrode. The protection spacer may have a bottom surface that is positioned at a level higher than that of a bottom surface of the lower electrode.
    Type: Application
    Filed: September 22, 2014
    Publication date: July 9, 2015
    Inventors: Jongchul Park, Hyungjoon Kwon, Joonkyu Rhee