Patents by Inventor Joonseok YANG

Joonseok YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Neuron device and integrated circuit including neuron device
    Patent number: 10832126
    Abstract: A neuron device may include an input unit, a synapse unit, and an output unit. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals and may generate an output signal based on the weighted sum.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 10, 2020
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jaeha Kim, Yunju Choi, Joonseok Yang, Seungheon Baek
  • NEURON DEVICE AND INTEGRATED CIRCUIT INCLUDING NEURON DEVICE
    Publication number: 20180300611
    Abstract: A neuron device is generally described. One exemplary neuron device may include an input unit, a synapse unit, and an output unit. The input unit can be configured to receive multiple input signals. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may include a floating gate metal oxide silicon field effect transistor (MOSFET) and may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals to which the coefficient information is applied and may generate an output signal based on the weighted sum.
    Type: Application
    Filed: October 1, 2015
    Publication date: October 18, 2018
    Inventors: Jaeha KIM, Yunju CHOI, Joonseok YANG, Seungheon BAEK