Abstract: A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.

Abstract: Provided is a reconfigurable logic device using an electrochemical potential. The device includes first and second semiconductor channels, where an effective magnetic field direction of a channel is controlled by a current direction and which are spaced apart from each other, a first ferromagnetic gate contacting the first semiconductor channel and a second ferromagnetic gate contacting the second semiconductor channel, where a magnetization direction is controlled by a gate voltage, and a control unit configured to calculate a difference value corresponding to a difference between a first determination value and a second determination value, and compare the difference value with a reference value to determine an output value.

Abstract: A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.

Abstract: A spin control electronic device operable at room temperature according to an embodiment of the present invention includes a transfer channel that includes a low-dimensional nanostructure, the nanostructure being located on a substrate, having an elongate shape in a first direction and having a cross section, cut along a second direction that is perpendicular to the first direction, in the shape of a triangle; a source electrode located on the substrate and intersecting the transfer channel, the source electrode covering part of the transfer channel; and a drain electrode spaced apart from the source electrode on the substrate, the drain electrode intersecting the transfer channel and covering part of the transfer channel.

Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.

Abstract: A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.

Abstract: A complementary device including a gate electrode, a channel, a source electrode connected to the gate electrode and the channel, and a first drain electrode and a second drain electrode connected to the gate electrode and the channel is provided. The first/second drain electrode is formed so that, in accordance with a voltage applied to the gate electrode, electron spins injected into the source electrode are moved from the source electrode to the first/second drain electrode through the channel while rotating in a first/second direction. Directions of the electron spins that reach the first drain electrode and the second drain electrode are opposite to each other.

Abstract: A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.

Abstract: A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained.

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract: There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Abstract: There is provided a complementary spin transistor logic circuit, including: a parallel spin transistor that includes a magnetized first source, a first drain magnetized in parallel with the magnetization direction of the first source, a first channel layer and a first gate electrode; and an anti-parallel spin transistor that includes a magnetized second source, a second drain magnetized in anti-parallel with the magnetization direction of the second source, a second channel layer and a second gate electrode, wherein the first gate electrode and the second gate electrode are connected to a common input terminal.

Abstract: A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

Abstract: A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.

Abstract: A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract: A magnetic memory device includes a substrate for reading and a magnetic memory cell. The substrate has a channel layer. The magnetic memory cell is formed on the substrate and has a magnetized magnetic material that transfers spin data to electrons passing the channel layer. Data stored in the magnetic memory cell are read by a voltage across both side ends of the channel layer that is generated when the electrons passing the channel layer deviate in the widthwise direction of the channel layer by a spin Hall effect.

Abstract: A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

Abstract: A spin transistor comprises a semiconductor substrate part having a lower cladding layer, a channel layer and an upper cladding layer sequentially stacked therein, a ferromagnetic source and drain on the substrate part, and a gate on the substrate part to control spins of electrons passing through the channel layer. The lower cladding layer comprises a first lower cladding layer and a second lower cladding layer having a higher band gap than that of the first lower cladding layer. The upper cladding layer comprises a first upper cladding layer and a second upper cladding layer having a higher band gap than that of the first upper cladding layer. The source and the drain are buried in an upper surface of the substrate part and extend downwardly to or under the first upper cladding layer.