Patents by Inventor Joon-Yong Choe

Joon-Yong Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11778810
    Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin A Kim, Ho-In Ryu, Kyo-Suk Chae, Joon Yong Choe
  • Patent number: 11574912
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
  • Publication number: 20220271044
    Abstract: A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride.
    Type: Application
    Filed: November 1, 2021
    Publication date: August 25, 2022
    Inventors: Seok Hyun Kim, Young Sin Kim, Dong Sik Park, Jong Min Lee, Joon Yong Choe
  • Publication number: 20220085028
    Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.
    Type: Application
    Filed: May 27, 2021
    Publication date: March 17, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin A KIM, Ho-In RYU, Kyo-Suk CHAE, Joon Yong CHOE
  • Publication number: 20210091086
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo HONG, Young-Ju LEE, Joon-Yong CHOE, Jung-hyun KIM, Sang-jun LEE, Hyeon-Kyu LEE, Yoon-Chul CHO, Je-Min PARK, Hyo-Dong BAN
  • Patent number: 10886277
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo Hong, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban
  • Publication number: 20190139963
    Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
    Type: Application
    Filed: August 21, 2018
    Publication date: May 9, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Augustin Jinwoo HONG, Young-Ju Lee, Joon-Yong Choe, Jung-Hyun Kim, Sang-Jun Lee, Hyeon-Kyu Lee, Yoon-Chul Cho, Je-Min Park, Hyo-Dong Ban