Patents by Inventor Joon-Young KWON

Joon-Young KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978911
    Abstract: The present invention relates to a three-dimensional structure electrode, a method for manufacturing same, and an electrochemical element including the electrode. The present invention is characterized by comprising: (a) an upper conductive layer and a lower conductive layer which have a structure constituting an assembly within which a conductive material and a porous nonwoven fabric including a plurality of polymeric fibers are three-dimensionally connected in an irregular and continuous manner, thereby forming a mutually connected porous structure; and (b) an active material layer forming the same assembly structure as the conductive layers and forming a three-dimensionally filled structure in which electrode active material particles are uniformly filled inside the mutually connected porous structure formed in the assembly structure, wherein the active material layer is formed between the upper conductive layer and the lower conductive layer.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: May 7, 2024
    Assignees: UNIST (Ulsan National Institute of Science and Technology), LG Energy Solution, Ltd.
    Inventors: In Sung Uhm, Sang Young Lee, Yo Han Kwon, Ju Myung Kim, Joon Won Lim, Jae Hyun Lee, Je Young Kim, Seong Hyeok Kim
  • Publication number: 20240125996
    Abstract: A method for replicating a holographic optical element and a holographic optical element replicated thereby are provided. The holographic optical element is larger than a master. The master has a holographic grating pattern generated on the master by interference of the reflected, diffracted or transmitted beam generated by irradiating the master having a specific diffraction grating pattern formed thereon with a laser beam.
    Type: Application
    Filed: August 25, 2021
    Publication date: April 18, 2024
    Applicant: LG Chem, Ltd.
    Inventors: Bo Ra Jung, Joon Young Lee, Min Soo Song, Do Kyeong Kwon, Yeon Jae Yoo
  • Patent number: 10916563
    Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin
  • Patent number: 10825934
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
  • Publication number: 20200203366
    Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.
    Type: Application
    Filed: June 26, 2019
    Publication date: June 25, 2020
    Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin
  • Publication number: 20200144427
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: JOON-YOUNG KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
  • Patent number: 10529865
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
  • Publication number: 20190035942
    Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.
    Type: Application
    Filed: April 27, 2018
    Publication date: January 31, 2019
    Inventors: Joon-Young KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE