Patents by Inventor Joon-young Oh
Joon-young Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951207Abstract: The present invention provides a stable liquid pharmaceutical formulation containing: an antibody or its antigen-binding fragment; a surfactant; a sugar or its derivative; and a buffer. The stable liquid pharmaceutical formulation according to the present invention has low viscosity while containing a high content of the antibody, has excellent long-term storage stability based on excellent stability under accelerated conditions and severe conditions, and may be administered subcutaneously.Type: GrantFiled: June 28, 2017Date of Patent: April 9, 2024Assignee: Celltrion Inc.Inventors: Joon Won Lee, Won Yong Han, Su Jung Kim, Jun Seok Oh, So Young Kim, Su Hyeon Hong, Yeon Kyeong Shin
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Patent number: 11927886Abstract: Disclosed are a substrate treating apparatus and a substrate treating method. According to an embodiment of the inventive concept, the purge operation of the purge nozzle is performed while the nozzle arm is moved from the first substrate support member to the second substrate support member, it hardly influences the operation of treating the substrate while the nozzle arm is moved from the first substrate support member to the second substrate support member. According to an embodiment of the inventive concept, the substrate treating apparatus may perform an operation of purging the photosensitive liquid nozzle while the treatment liquid supply unit performs a process of supplying the photosensitive liquid to the substrate. Accordingly, because the operation of purging the photosensitive liquid nozzle is performed at the same time when the substrate treating apparatus performs a process, productivity may be improved.Type: GrantFiled: March 5, 2021Date of Patent: March 12, 2024Assignee: SEMES CO., LTD.Inventors: Doo Young Oh, Joon Jae Lee
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Patent number: 10204892Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.Type: GrantFiled: June 14, 2017Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
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Publication number: 20170358564Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.Type: ApplicationFiled: June 14, 2017Publication date: December 14, 2017Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
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Patent number: 9684345Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.Type: GrantFiled: November 22, 2013Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-young Choi, Joon-young Oh, Hee-youb Kang, Jung-hoon Kim, Won-hwa Lee, Jae-beom Byun, Jong-yun Yun
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Patent number: 8838885Abstract: Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.Type: GrantFiled: June 7, 2012Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ok Kwak, Sang-sub Song, Sang-ho An, Joon-young Oh, Jeong-sik Yoo
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Patent number: 8791554Abstract: A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.Type: GrantFiled: June 22, 2012Date of Patent: July 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ok Kwak, Sang-Sub Song, Sang-Ho An, Joon-Young Oh
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Publication number: 20140146461Abstract: A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.Type: ApplicationFiled: November 22, 2013Publication date: May 29, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-young Choi, Joon-young Oh, Hee-youb Kang, Jung-hoon Kim, Won-hwa Lee, Jae-beom Byun, Jong-yun Yun
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Publication number: 20130020685Abstract: A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.Type: ApplicationFiled: June 22, 2012Publication date: January 24, 2013Inventors: Dong-Ok KWAK, Sang-Sub Song, Sang-Ho An, Joon-Young Oh
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Publication number: 20120317332Abstract: Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.Type: ApplicationFiled: June 7, 2012Publication date: December 13, 2012Inventors: Dong-ok Kwak, Sang-sub Song, Sang-ho An, Joon-young Oh, Jeong-sik Yoo
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Patent number: 8178960Abstract: Provided is a stacked semiconductor package and a method of manufacturing the same. The stacked semiconductor package may include a first semiconductor package, a second semiconductor package, and at least one electrical connection device electrically connecting the first and second semiconductor packages. The first semiconductor package may include a first re-distribution pattern on a first semiconductor chip and a first sealing member on the first substrate, the first sealing member may include at least one first via to expose the first re-distribution pattern. The second semiconductor package may include a second re-distribution pattern on a second semiconductor chip and a second sealing member on a lower side of the second substrate, the second sealing member may include at least one second via to expose the second re-distribution pattern. An electrical connection device may be between the first and second vias to connect the first and the second re-distribution patterns.Type: GrantFiled: March 4, 2010Date of Patent: May 15, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Joon-young Oh
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Publication number: 20120068306Abstract: A semiconductor package includes a packaging substrate including a first bond finger and a second bond finger, a first semiconductor chip mounted on the packaging substrate, and including a first chip pad and a second chip pad, the first bond finger being electrically connected to the first chip pad by a first bonding wire, and the second bond finger being electrically connected to the second chip pad by a second bonding wire, and a first decoupling semiconductor capacitor mounted on the first semiconductor chip, and including a first capacitor pad, the first capacitor pad being electrically connected to the second chip pad.Type: ApplicationFiled: September 13, 2011Publication date: March 22, 2012Inventors: Sang-Sub SONG, Sung-Hoon Chun, Sang-Ho An, Joon-Young Oh, Dong-Ok Kwak
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Publication number: 20120061816Abstract: Provided are a semiconductor package and method of fabricating the same. The package includes an interconnection substrate, a semiconductor chip mounted on the interconnection substrate, a lateral wire bonded on the interconnection substrate and configured to enclose a side surface of the semiconductor chip, and a metal layer disposed on the semiconductor chip and electrically connected to the lateral wire.Type: ApplicationFiled: September 8, 2011Publication date: March 15, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-Sub SONG, Sang-Ho An, Joon-Young Oh, Dong-Ok Kwak, Joon-Ki Park
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Publication number: 20100258930Abstract: Provided is a stacked semiconductor package and a method of manufacturing the same. The stacked semiconductor package may include a first semiconductor package, a second semiconductor package, and at least one electrical connection device electrically connecting the first and second semiconductor packages. The first semiconductor package may include a first re-distribution pattern on a first semiconductor chip and a first sealing member on the first substrate, the first sealing member may include at least one first via to expose the first re-distribution pattern. The second semiconductor package may include a second re-distribution pattern on a second semiconductor chip and a second sealing member on a lower side of the second substrate, the second sealing member may include at least one second via to expose the second re-distribution pattern. An electrical connection device may be between the first and second vias to connect the first and the second re-distribution patterns.Type: ApplicationFiled: March 4, 2010Publication date: October 14, 2010Inventor: Joon-young Oh