Abstract: An overvoltage protection device includes first and second semiconductor devices arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, a first terminal connection to a terminal of the first semiconductor device that is opposite from the central node, a second terminal connection to a terminal of the second semiconductor device that is opposite from the central node. A total capacitance of elements in a first transmission path that is between the first terminal connection and the central node substantially matches a total capacitance of elements in a second transmission path that is between the second terminal connection and the central node. The total capacitance of elements in the second transmission path includes a self-capacitance of the conductive link.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

Abstract: An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.

Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.

Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.

Abstract: A semiconductor device includes a semiconductor body, first and second contact pads disposed on an upper surface of the semiconductor body, a lateral ESD protection device formed in the semiconductor body, and a vertical ESD protection device formed in the semiconductor body, wherein the lateral ESD protection device and the vertical ESD protection device together form a unidirectional device between the first and second contact pads, and wherein the lateral ESD protection device is formed in a first portion of the semiconductor body that is laterally electrically isolated from a vertical current path of the vertical ESD protection device.

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Abstract: A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m1, with m1?0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m12. The first partial junction grading coefficient m11 is different to the second partial junction grading coefficient m12, with m11?m12. At least one of the first and second partial junction grading coefficients m11, m12 is greater than 0.50, with m11 and/or m12>0.50. The first junction grading coefficient m1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m11, m12.

Abstract: An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: An overvoltage protection device includes first and second semiconductor devices arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, a first terminal connection to a terminal of the first semiconductor device that is opposite from the central node, a second terminal connection to a terminal of the second semiconductor device that is opposite from the central node. A total capacitance of elements in a first transmission path that is between the first terminal connection and the central node substantially matches a total capacitance of elements in a second transmission path that is between the second terminal connection and the central node. The total capacitance of elements in the second transmission path includes a self-capacitance of the conductive link.

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m1, with m1?0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m12. The first partial junction grading coefficient m11 is different to the second partial junction grading coefficient m12, with m11?m12. At least one of the first and second partial junction grading coefficients m11, m12 is greater than 0.50, with m11 and/or m12>0.50. The first junction grading coefficient m1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m11, m12.