Patents by Inventor Joost J. M. Waeterloos

Joost J. M. Waeterloos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
    Patent number: 7115531
    Abstract: This invention is a method comprising providing a substrate, forming a first layer on the substrate, wherein the first layer has a dielectric constant of less than 3.0 and comprises an organic polymer, applying an organosilicate resin over the first layer, removing a portion of the organosilicate resin to expose a portion of the first layer, and removing the exposed portions of the first layer. The invention is also an integrated circuit article comprising an active substrate containing transistors and an electrical interconnect structure containing a pattern of metal lines separated, at least partially, by layers or regions of an organic polymeric material having a dielectric constant of less than 3.0 and further comprising a layer of an organosilicate resin above at least one layer of the organic polymer material.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: October 3, 2006
    Assignee: Dow Global Technologies Inc.
    Inventors: Edward O. Shaffer, II, Kevin E. Howard, Joost J. M. Waeterloos, Jack E. Hetzner, Paul H. Townsend, III, Lynne K. Mills, Sheila Gombar-Fetner, Larry R. Wilson
  • Tri-layer masking architecture for patterning dual damascene interconnects
    Patent number: 6815333
    Abstract: This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 9, 2004
    Assignee: Dow Global Technologies Inc.
    Inventors: Paul H. Townsend, III, Lynne K. Mills, Joost J. M. Waeterloos, Richard J. Strittmatter
  • Tri-layer masking architecture for patterning dual damascene interconnects
    Publication number: 20030219973
    Abstract: This invention relates to a method of dual damascene integration for manufacture of integrating circuits using three top hard mask layers having alternating etch selectivity characteristics.
    Type: Application
    Filed: March 28, 2003
    Publication date: November 27, 2003
    Inventors: Paul H. Townsend, Lynne K. Mills, Joost J. M. Waeterloos, Richard J. Strittmatter
  • Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
    Publication number: 20020052125
    Abstract: This invention is a method comprising providing a substrate, forming a first layer on the substrate, wherein the first layer has a dielectric constant of less than 3.0 and comprises an organic polymer, applying an organosilicate resin over the first layer, removing a portion of the organosilicate resin to expose a portion of the first layer, and removing the exposed portions of the first layer. The invention is also an integrated circuit article comprising an active substrate containing transistors and an electrical interconnect structure containing a pattern of metal lines separated, at least partially, by layers or regions of an organic polymeric material having a dielectric constant of less than 3.0 and further comprising a layer of an organosilicate resin above at least one layer of the organic polymer material.
    Type: Application
    Filed: August 20, 2001
    Publication date: May 2, 2002
    Inventors: Edward O. Shaffer, Kevin E. Howard, Joost J.M. Waeterloos, Jack E. Hetzner, Paul H. Townsend, Lynne K. Mills, Sheila Gombar-Fetner, Larry R. Wilson