Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Abstract: A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.

Abstract: A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

Abstract: A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

Abstract: A trench power semiconductor component is described which has an edge cell in which an edge trench is provided. The edge trench, at least on an outer side wall, has a thicker insulating layer than an insulating layer of trenches of the cell array. This simple configuration provides a high dielectric strength and is economical to produce.

Abstract: A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

Abstract: A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

Abstract: A method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. The field effect-controllable semiconductor component has a semiconductor substrate of a first conductivity type and a gate insulator layer on the surface of the semiconductor substrate. A well of a second conductivity type is produced in the semiconductor substrate by implanting first impurity atoms. A semiconductor layer having a first predetermined thickness is produced on the gate insulator layer prior to the production of the well. The semiconductor layer is reduced in a predtdermined region to obtain a residual layer having a second predetermined thickness, such that the semiconductor layer acts as an implantation barrier outside the predetermined region when the well is produced.

Abstract: A circuit configuration for protecting electronic circuits against overload of a supply voltage source includes a voltage-limiting configuration, such as a Zener diode. A depletion layer field effect transistor is connected upstream of the voltage-limiting configuration and has interconnected gate and source terminals.