Patents by Inventor Joost Vlassak

Joost Vlassak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8265884
    Abstract: A method of measuring the elastic modulus and hardness of a thin film on substrate using nanoindentation technique is provided. The method includes calculating a series of experimental corrected stiffness and contact radius pairs associated with one or more presumed parameters and information obtained from a loading curve associated with the thin film and substrate. Also, the method includes calculating a series of theoretical corrected stiffness and contact radius pairs associated with the same one or more presumed parameters and information obtained from the loading curve associated with the thin film and substrate. Furthermore, the method includes using results obtained from the experimental and theoretical corrected stiffness and contact radius pairs to compute the elastic modulus and hardness of the film material.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: September 11, 2012
    Assignee: President and Fellows of Harvard College
    Inventors: Han Li, Joost Vlassak
  • Publication number: 20100024534
    Abstract: A method of measuring the elastic modulus and hardness of a thin film on substrate using nanoindentation technique is provided. The method includes calculating a series of experimental corrected stiffness and contact radius pairs associated with one or more presumed parameters and information obtained from a loading curve associated with the thin film and substrate. Also, the method includes calculating a series of theoretical corrected stiffness and contact radius pairs associated with the same one or more presumed parameters and information obtained from the loading curve associated with the thin film and substrate. Furthermore, the method includes using results obtained from the experimental and theoretical corrected stiffness and contact radius pairs to compute the elastic modulus and hardness of the film material.
    Type: Application
    Filed: July 21, 2009
    Publication date: February 4, 2010
    Inventors: Han Li, Joost Vlassak
  • Publication number: 20070286769
    Abstract: A calorimetric system includes a plurality of cell structures being used to define a selective region for calorimetric measurements of a nano-structure. Heating units are positioned on the cell structures to provide the necessary energy needed to perform calorimetric measurements in each of the cell structures. The cell structures and the heating units are arranged so as to allow the calorimetric system to perform, in combinatorial fashion, calorimetric measurements associated with the nano-structure.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 13, 2007
    Inventors: Joost Vlassak, Patrick McCluskey
  • Publication number: 20050233264
    Abstract: Methods of reducing the intrusions or migrations of photolithography materials by introducing a sol-gel layer onto a porous thin film prior to applying the photolithography/photoresist material layer. Curing the sol-gel layer results in the sol-gel layer merging or unifying with the underlying porous thin film layer so that the combined sol-gel/thin layer exhibits substantially the same properties as the untreated porous thin film layer before the sol-gel was applied. As a result, a greater etching accuracy is achieved.
    Type: Application
    Filed: June 17, 2005
    Publication date: October 20, 2005
    Applicant: Xerox Corporation
    Inventors: James Zesch, Joost Vlassak
  • Patent number: 6319727
    Abstract: A process for manufacturing metallic interconnect lines of low stress. Process steps according to the present invention first include a step of providing a semiconductor substrate (e.g. a silicon wafer) with an overlying insulating layer, followed by forming a multi-layer stack on the insulating layer. The multi-layer stack includes at least two adjoining layers: one being a metal M layer (for example an aluminum layer) and the other being a material Q layer, where material Q is a material that forms either (i) an electrically conductive intermetallic layer, or (ii) an electrically conducting solid solution layer, with metal M when subjected to the subsequent thermal treatment step. Silicon and titanium meet this requirement when metal M is aluminum. The multi-layer stack is then pattered to form a multi-layer metallic interconnect line. An interconnect dielectric material layer (e.g.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: November 20, 2001
    Assignee: National Semiconductor Corporation
    Inventor: Joost Vlassak