Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Abstract: An apparatus for anonymizing personal information according to an embodiment may include an encoder configured to generate an input latent vector by extracting a feature of input data, a generator configured to generate reconstructed data by demodulating a predetermined content vector based on a style vector generated based on the input latent vector, and a discriminator configured to discriminate genuine data and fake data by receiving the reconstructed data and real data.

Abstract: The invention refers to a method for manufacturing an electrode assembly for a battery cell, whereat segments of a first electrode are placed between a continuous first separator sheet and a continuous second separator sheet; segments of a second electrode are placed on an opposite side of the first separator sheet in respect of the segments of the first electrode and on an opposite side of the second separator sheet in respect of the segments of the first electrode such that a tape element is formed; and the tape element is folded such that the segments of the first electrode and the segments of the second electrode are aligned in a stacking direction. The invention also refers to a battery cell, in particular a lithium ion battery cell, comprising an electrode assembly manufactured using the method according to the invention.

Abstract: The invention describes a method (10) for producing a positive electrode for a battery cell, comprising an active material and a conductive additive, wherein the active material has a first number of, in particular spherical, active material particles with a first mean diameter, and wherein the conductive additive has a second number of, in particular spherical, conductive additive particles with a second mean diameter, wherein the active material and the conductive additive are provided in a first method step (102), wherein the number of conductive additive particles is adjusted depending on a ratio of the second mean diameter to the first mean diameter and on the number of active material particles.

Abstract: The invention relates to an electrode of a battery cell, in particular a positive electrode of a lithium-ion battery cell, in the present case in the form of an electrode layer (102, 202, 302) and comprising an active material having a plurality of active material particles (106, 206, 306), characterised in that a thickness of the electrode layer (102, 202, 302) is at least twice as large as a maximum diameter of the active material particles (106, 206, 306).

Abstract: The invention relates to a solid electrolyte material (1) for an electrochemical cell (10), particularly a lithium ion battery cell, comprising: at least one garnet-type lithium ion-conducting solid electrolyte (2), and at least one coating material (3), which is applied to at least a part of the surface of the garnet-type lithium ion-conducting solid electrolyte (2), the at least one coating material (3) comprising at least one lithium ion-conducting compound, which is chemically stable against air and humidity. The invention further relates to a method for producing the solid electrolyte material (1), the use thereof, and an electrochemical cell (10) comprising the solid electrolyte material (1).

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Abstract: A display device includes: a first substrate including a display area; a thin film transistor positioned on the first substrate; a pixel electrode connected to the thin film transistor; a color filter overlapping the pixel electrode; a second substrate overlapping the first substrate; a liquid crystal layer positioned between the first substrate and the second substrate; and a stain correction layer positioned between the second substrate and the liquid crystal layer and including a semiconductor nanocrystal. The display area includes a first region and a second region excluding the first region. The stain correction layer is positioned in the first region.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.

Abstract: A composite film (1) comprising a composition comprising at least one solid electrolyte and at least one binder, wherein the fraction of binder in the composition increases with decreasing distance from the margins (30, 31) of the composite film (1). Also a method for producing a composite film (1) of this kind, to the use thereof, and also a solid-state electrochemical cell comprising a composite film (1) of this kind.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip.

Abstract: The present invention relates to a positive electrode for a secondary battery in which a maximum diameter of internal pores is controlled to be less than 1 ?m, a method of preparing the same, and a secondary battery including the positive electrode.

Abstract: The invention refers to a method for manufacturing an electrode assembly for a battery cell, whereat segments of a first electrode are placed between a continuous first separator sheet and a continuous second separator sheet; segments of a second electrode are placed on an opposite side of the first separator sheet in respect of the segments of the first electrode and on an opposite side of the second separator sheet in respect of the segments of the first electrode such that a tape element is formed; and the tape element is folded such that the segments of the first electrode and the segments of the second electrode are aligned in a stacking direction. The invention also refers to a battery cell, in particular a lithium ion battery cell, comprising an electrode assembly manufactured using the method according to the invention.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.