Patents by Inventor Jooyub KIM

Jooyub KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices including a liner and method of manufacturing the same
    Patent number: 11812607
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Donghyun Im, Jooyub Kim, Juhyung We, Namhoon Lee, Chunhyung Chung
  • Semiconductor devices having an insulation layer in a recess and an impurity barrier layer extending along the insulation layer
    Patent number: 11742401
    Abstract: A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: August 29, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungmi Yoon, Jooyub Kim, Daehyun Kim, Juhyung We, Donghyun Im, Chunhyung Chung
  • SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220189963
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sungmi YOON, Donghyun IM, Jooyub KIM, Juhyung WE, Namhoon LEE, Chunhyung CHUNG
  • SEMICONDUCTOR DEVICES
    Publication number: 20220181457
    Abstract: A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.
    Type: Application
    Filed: June 7, 2021
    Publication date: June 9, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sungmi YOON, Jooyub KIM, Daehyun KIM, Juhyung WE, Donghyun IM, Chunhyung CHUNG
  • Semiconductor devices including a silicon liner on an active pattern and method of manufacturing the same
    Patent number: 11296089
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Donghyun Im, Jooyub Kim, Juhyung We, Namhoon Lee, Chunhyung Chung
  • SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210091085
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Application
    Filed: April 16, 2020
    Publication date: March 25, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sungmi YOON, Donghyun IM, Jooyub KIM, Juhyung WE, Namhoon LEE, Chunhyung CHUNG