Abstract: An apparatus includes a memory controller and scrambling circuitry. The memory controller is configured to control a Dynamic Random-Access Memory (DRAM). The scrambling circuitry is configured to maintain one or more scrambling keys associated with one or more active rows of the DRAM, respectively, to identify a memory-access command, which is transferred between the memory controller and the DRAM and which addresses a given active row of the DRAM, and to apply to the command a scrambling key that is associated with the given active row.

Abstract: A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Abstract: A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Abstract: Apparatus for display processing includes a host interface, which is arranged to accept graphical information from a first computer. A first display head is arranged to produce a first digital video signal including first frames representing the graphical information at a first frame rate, for displaying the graphical information on a local display of the first computer. A second display head is arranged to produce a second digital video signal including second frames representing the graphical information at a second frame rate that is lower than the first frame rate. A video redirection module is arranged to regulate a transmission rate of the second digital video signal from the second display head, to capture the second frames that are generated by the second display head and to forward the captured frames to a second computer.

Abstract: A method for capturing images includes associating the pixels with tiles. An input data sequence representing respective current values of the pixels of a currently-captured image frame is accepted. Within each of at least some of the tiles, the current values are compared with respective reference values of the pixels of a reference frame stored in a frame buffer in order to detect variations between the current and reference values. When a variation is detected at a given pixel, the current value is written into the frame buffer in place of a corresponding reference value, and the tile is marked as a changed tile. Subsequent pixel values belonging to the changed tile are written into the frame buffer without comparing the current values of the subsequent pixels to the respective reference values, thereby replacing the reference frame with the currently-captured image frame.

Abstract: A method for capturing images includes associating the pixels with tiles. An input data sequence representing respective current values of the pixels of a currently-captured image frame is accepted. Within each of at least some of the tiles, the current values are compared with respective reference values of the pixels of a reference frame stored in a frame buffer in order to detect variations between the current and reference values. When a variation is detected at a given pixel, the current value is written into the frame buffer in place of a corresponding reference value, and the tile is marked as a changed tile. Subsequent pixel values belonging to the changed tile are written into the frame buffer without comparing the current values of the subsequent pixels to the respective reference values, thereby replacing the reference frame with the currently-captured image frame.