Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate. The second transistor is disposed on the substrate. A gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages.

Abstract: A Static Random Access Memory (SRAM) Cell includes a first gate electrode layer covering a channel region of a read pull-down transistor, a second gate electrode layer covering channel regions of a first pull-down transistor and a first pull-up transistor, a third gate electrode layer covering a channel region of a second pass-gate transistor, a fourth gate electrode layer covering a channel region of a read pass-gate transistor, a fifth gate electrode layer covering a channel region of a first pass-gate transistor, and a sixth gate electrode layer covering channel regions of a second pull-down transistor and a second pull-up transistor. The first and second gate electrode layers are separated from each other by a first dielectric layer interposed therebetween, and are electrically connected to each other by a first interconnection layer formed thereon.

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate. The second transistor is disposed on the substrate. A gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages.

Abstract: A Static Random Access Memory (SRAM) Cell includes a first gate electrode layer covering a channel region of a read pull-down transistor, a second gate electrode layer covering channel regions of a first pull-down transistor and a first pull-up transistor, a third gate electrode layer covering a channel region of a second pass-gate transistor, a fourth gate electrode layer covering a channel region of a read pass-gate transistor, a fifth gate electrode layer covering a channel region of a first pass-gate transistor, and a sixth gate electrode layer covering channel regions of a second pull-down transistor and a second pull-up transistor. The first and second gate electrode layers are separated from each other by a first dielectric layer interposed therebetween, and are electrically connected to each other by a first interconnection layer formed thereon.