Abstract: A processor system comprising a number of data handling units interconnected by a system bus operates according to a novel protocol wherein one of the number of data handling units issues a buss request signal together with a separate arbitration signal uniquely identifying the data handling unit requesting access to the system bus. Distributed priority determination logic, located in each data handling unit, allows each data handling unit requesting bus access at the same moment in time to independently and unilaterally ascertain who has access. The bus request signal remains asserted to hold off any additional requests for bus access until all data handling units first requesting access have been serviced.

Abstract: A high speed, synchronous, processor bus is physically and electrically extended by a bus extension unit to provide data communication between a number of data handling units. The bus extension unit intercouples a system bus to an extended buses for communicating information therebetween. The extension monitors both bus and, upon recognition of an initiation for an information transfer transaction from one bus to the other, will relay the initiation of the transaction, implement the transaction, then relay back any handshake signals that form a part of the transaction, all with a minimum delay of one bus cycle.

Abstract: A memory system is implemented by an array of large scale integrated dynamic random access memory elements. The memory elements are of a type that permit data way word storage on a page basis, each page being defined on a row boundary. Discovering that excess power consumption by the memory can result from successive memory operations made back-to-back to different page locations, the present invention provides counter means to count each immediately successive different page memory operations so that, when that count matches a maximum count, memory operations are stalled for a period of time.

Abstract: A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal.

Abstract: A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated.