Patents by Inventor Jordan Swartz

Jordan Swartz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 11755810
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 12, 2023
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • METHOD AND APPARATUS FOR PERFORMING PARALLEL ROUTING USING A MULTI-THREADED ROUTING PROCEDURE
    Publication number: 20210073453
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 11, 2021
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 10783310
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 22, 2020
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • METHOD AND APPARATUS FOR PERFORMING PARALLEL ROUTING USING A MULTI-THREADED ROUTING PROCEDURE
    Publication number: 20190108303
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: October 8, 2018
    Publication date: April 11, 2019
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 10140411
    Abstract: A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 27, 2018
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices
    Publication number: 20170337318
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Application
    Filed: July 30, 2017
    Publication date: November 23, 2017
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
    Patent number: 9754065
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 5, 2017
    Assignee: Altera Corporation
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
    Publication number: 20170068768
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 9536034
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 3, 2017
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
    Patent number: 9443054
    Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: September 13, 2016
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
    Publication number: 20150154338
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 4, 2015
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 8935650
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: January 13, 2015
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure
    Publication number: 20140223403
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
    Patent number: 8745566
    Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 3, 2014
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 8739105
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: May 27, 2014
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices
    Publication number: 20140047405
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 13, 2014
    Applicant: Altera Corporation
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and Apparatus for Performing Parallel Routing Using A Multi-Threaded Routing Procedure
    Publication number: 20130318491
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Application
    Filed: August 2, 2013
    Publication date: November 28, 2013
    Applicant: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices
    Patent number: 8589849
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 19, 2013
    Assignee: Altera Corporation
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    Patent number: 8533652
    Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 10, 2013
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
    Patent number: 8443325
    Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 14, 2013
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Caroline Pantofaru, Jordan Swartz