Abstract: A system and method for reducing central processing unit transistor count when dividing multiple floating point numbers is disclosed. An example system may receive a plurality of floating point numbers to be inverted as denominator values. The denominator values may be grouped into pairs and multiplied. Products of pairs may be multiplied to produce combinations of products of denominator values until all denominator values have been multiplied together. The product of all denominator values may be inverted using a single division. The combinations of products of denominator values from the multiplications achieved before the division may be multiplied with the inverted product from the division to compute inversions of all denominator values. In some embodiments, an example system may receive a plurality of floating point numbers as numerator values that each correspond to a denominator value. Numerator values may be multiplied with corresponding inversion denominator values to produce division results.

Abstract: A system and method for reducing central processing unit usage when inverting or dividing multiple floating point numbers is disclosed. An example system may receive a plurality of floating point numbers to be inverted as denominator values. The denominator values may be grouped into pairs and multiplied. Products of pairs may be multiplied to produce combinations of products of denominator values until all denominator values have been multiplied together. The product of all denominator values may be inverted using a single division. The combinations of products of denominator values from the multiplications achieved before the division may be multiplied with the inverted product from the division to compute inversions of all denominator values. In some embodiments, an example system may receive a plurality of floating point numbers as numerator values that each correspond to a denominator value. Numerator values may be multiplied with corresponding inversion denominator values to produce division results.

Abstract: In a computer system, a cross-compiler converts non-native code into native code immediately prior to execution of that code. The system also includes a code cache for storing cross-compiled code and a hash table for locating code blocks in the code cache. In a preferred embodiment, the system also includes an interpreter for emulating certain non-native instructions that are not converted into native code by the cross-compiler. While executing any non-native application, if the next instruction is not one of the predefined set of non-native instructions to be handled by interpretation or a special purpose procedure, then the next instruction is considered to be an "entry point" instruction, and the cross-compiler looks up the address of the entry point instruction in the hash table to see if a corresponding native code block is already stored in the code cache. If so, the native code block in the code cache is executed until an exit instruction in the native code block is encountered.

Abstract: A virtual memory system and method enable a computer system to use a virtual memory address space larger than the size of physical primary memory while swapping few, if any, pages out to secondary memory. Primary memory is divided into a work space, used for storing uncompressed pages in current use, and a "Compression Heap". A MappedOut storage space, which includes the Compression Heap and a portion of secondary memory, is used to store all pages swapped out of the work space. A virtual memory manager dynamically determines the number of pages of primary memory which need to be included in the work space, and moves pages of primary memory into the work space from the Compression Heap as needed. Pages are selected to be swapped out of the work space to the MappedOut storage space on the basis of memory usage data.