Abstract: A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.

Abstract: P-type multi gate field effect transistor access devices are adapted to be coupled to a memory cell to provide access to the memory cell. A method is described that uses a power switch to switch off address decoding circuitry allowing word lines to float toward a high supply voltage, turning off the p-type multi gate field effect transistor access devices.

Abstract: A multi-gate field effect transistor power switch is used to selectively couple a circuit to a supply voltage. In various embodiments, both n and p-type multi-gate field effect transistor power switches may be used to couple sub-circuits of varying granularity to different voltage supplies.

Abstract: A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Abstract: An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.

Abstract: A digital circuit unit includes at least one circuit block, a voltage source for supplying the circuit block, a detection unit, which monitors the change of current drain by the at least one circuit block, an additional power consumption unit, which upon activation consumes power in addition to the at least one circuit block, and a control unit, which controls the power consumption unit in such a way that upon a change in the power consumption of the circuit block the power consumption unit is activated and drains current.

Abstract: A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK) resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) an which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (Clk<SB>DELAY</SB>) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage.

Abstract: A semiconductor device detects and adjusts leakage current dependent on threshold voltage of an integrated semiconductor device. To adjust the threshold voltage variation due to uncertainties in the channel length induced by the fabrication process (short channel effect) in the semiconductor a comparison between small and long channel devices is proposed. According to the comparison result, a bias potential is provided to the semiconductor device to adjust the threshold voltage.

Abstract: Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.

Abstract: Methods and devices for saving and/or setting a circuit state of a microelectronic circuit that includes at least one scan chain for testing the circuit are disclosed. In this connection, the at least one scan chain is used to save and/or set the circuit state, as a result of which an expansion of the circuit is unnecessary.

Abstract: A semiconductor device detects and adjusts leakage current dependent on threshold voltage of an integrated semiconductor device. To adjust the threshold voltage variation due to uncertainties in the channel length induced by the fabrication process (short channel effect) in the semiconductor a comparison between small and long channel devices is proposed. According to the comparison result, a bias potential is provided to the semiconductor device to adjust the threshold voltage.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is placed on the substrate surface of a substrate. The coil comprises one or more windings, whereby the winding(s) is/are formed by at least segments of two conductor tracks, which are each provided in spatially spaced-apart metalization levels, and by via-contacts which connect these conductor track(s) and/or conductor track segments. In order to be able to produce high-quality coils, a coil is produced with the largest possible coil cross-section, whereby a standard metalization, especially a standard metalization using copper, can, however, be used for producing the oil. To this end, the via contacts are formed from a stack of two ore more via elements arranged one above the other. Parts of the metalization levels can be located between the via elements.

Abstract: In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.