Abstract: A multiplication circuit for binary coded numbers uses rows of adders and multipliers for parallel computation. Sign bit supplementation is used in which sign bits are supplemented by binary digits in the rows of adders. In particular, the required addition of the sign bit first occurs in the first multiplier row where elements representing simple loads are used in place of adders with inputs that represent multiple input loads. Wiring simplification also is applied in the higher order adders of subsequent adder rows. Circuit simplification is achieved by replacing half adders with inverters.