Abstract: Systems and methods are disclosed for a neural interface. In one implementation, a neural interface comprises a neural probe configured for placement within a brain; at least one signal lead extending from the neural probe; and a sensing assembly included on the neural probe, where the sensing assembly includes: a plurality of dual-role electrodes positioned on the neural probe, wherein each of the dual-role electrodes is configured to sense electrical signals generated by one or more neurons in the brain and to convey to the at least one signal lead one or more sense signals generated based on the sensed electrical signals, and wherein each of the dual-role electrodes is configured to receive, via the at least one signal lead, a stimulation signal selectively delivered from a stimulus generator.

Abstract: In exemplary implementations of this invention, electrical connections are fabricated between two orthogonal surfaces by electroplating. The two surfaces are separated (except for the electrical connections) by a gap of not more than 100 micrometers. Multiple electrical connections may be fabricated across the gap. In preparatory steps, conductive pads on the two surfaces may be separately electroplated to build up “bumps” that make it easier to bridge the remainder of the gap in a final plating step. Alternately, electroless deposition may be used instead of electroplating. In exemplary implementations, a 3D probe array may be assembled by inserting array structures into an orthogonal base plate. The array structures may be aligned and held in place, relative to the base plate, by mechanical means, including side hooks, stabilizers, bottom hooks, alignment parts and a back plate.

Abstract: In exemplary implementations of this invention, high-throughput screening of a mammalian brain is performed to locate neural circuit targets of interest. A variety of search patterns may be used for this neural screening, including (a) iterative subdivision, (b) serial search, and (c) combinatorial. To perform this neural screening, an array of optical fibers (or an array of waveguides) is inserted into the brain. Alternately, the array is positioned adjacent to the brain. Each fiber or waveguide in the array is coupled to a light source (LED or laser). The brain has been previously sensitized to light, using genetically encoded optical neural control reagents, which are delivered either using viruses or via transgenic means. In the screening, the array is used to optically perturb the brain. For example, the neurons of the brain may be activated by one color of light, and/or silenced by another color of light.

Abstract: In exemplary implementations of this invention, electrical connections are fabricated between two orthogonal surfaces by electroplating. The two surfaces are separated (except for the electrical connections) by a gap of not more than 100 micrometers. Multiple electrical connections may be fabricated across the gap. In preparatory steps, conductive pads on the two surfaces may be separately electroplated to build up “bumps” that make it easier to bridge the remainder of the gap in a final plating step. Alternately, electroless deposition may be used instead of electroplating. In exemplary implementations, a 3D probe array may be assembled by inserting array structures into an orthogonal base plate. The array structures may be aligned and held in place, relative to the base plate, by mechanical means, including side hooks, stabilizers, bottom hooks, alignment parts and a back plate.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: In exemplary implementations of this invention, high-throughput screening of a mammalian brain is performed to locate neural circuit targets of interest. A variety of search patterns may be used for this neural screening, including (a) iterative subdivision, (b) serial search, and (c) combinatorial. To perform this neural screening, an array of optical fibers (or an array of waveguides) is inserted into the brain. Alternately, the array is positioned adjacent to the brain. Each fiber or waveguide in the array is coupled to a light source (LED or laser). The brain has been previously sensitized to light, using genetically encoded optical neural control reagents, which are delivered either using viruses or via transgenic means. In the screening, the array is used to optically perturb the brain. For example, the neurons of the brain may be activated by one color of light, and/or silenced by another color of light.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.