Abstract: In a circuit arrangement for the control of semi-duplex data transmission systems, which operate in accordance with crypto techniques, and in which the data of a data source are supplied to a data terminal by way of a transmission side crypto device, a transmission path and a receiving side crypto device, the data of the data source are supplied to a transmitting side shift register and a serially processed toward the receiving side crypto device by way of an output of the shift register and the transmitting side crypto device, and an order evaluator is connected to a number of cells of the shift register to produce a reset signal if an order word occurs, the reset signal causing erasure of the content of the individual, or all, cells of the shift register.