Abstract: A compute fabric includes, in part, a multitude of compute blocks, a networking circuit adapted to enable communication between the multitude of compute blocks, a performance monitor, and a controller trained to configure the compute fabric. The controller may be trained using a reinforcement learning process by setting the compute fabric to a first state, receiving a measurement of the performance characteristic of the compute fabric from performance monitor, receiving a reward signal in response to the measured performance characteristic; and repeating the setting, the receiving of the measurement and the receiving of the reward signal until the received reward reaches a maximum value. Each of at least a first subset of the compute blocks may be an analog in-memory compute block. Each of at least a second subset of the compute blocks may be a digital compute block.

Abstract: A single-ended successive approximation register (SAR) digital-to-analog converter (ADC) includes, in part, an array of N capacitors each having a first plate coupled to a first node. A second plate of each of the N capacitors is coupled to an associated one of N different switches configured to connect the second plate of the capacitor to a ground voltage or a reference voltage. The SAR ADC also includes a comparator having a first input receiving the voltage of the first node, and a second input that receives the reference voltage if the voltage at the first node during a first phase is smaller than the reference voltage. The second input to the comparator receives twice the reference voltage if the voltage at the first node during the first phase is greater than the reference voltage.

Abstract: A capacitive multiplier includes, in part, a multitude of capacitors disposed along S rows and T columns. The capacitors disposed in the ith column are coupled to one another and are configured to be coupled to or uncoupled from capacitors disposed in the column T via an ith switch, where i ranges from 1 to (T-1). The capacitive multiplier further includes, in part, a timing controller configured to generate (T-1) control signals each of which is associated with one of (T-1) switches. The timing controller generates the (T-1) control signals in sequence such that the ith switch is closed before (i+1)th switch opens, and the ith switch is opened before closing the (i+1)th switch. In response to closing of the ith switch, the capacitors in the ith column are coupled to capacitors in column T to share and distribute their charges.

Abstract: A compute fabric includes, in part: a multitude of compute tiles disposed in a memory block, a networking circuit coupled to the compute tiles and adapted to enable communication between the compute tiles and further to enable the compute tiles to communicate with a system external to the compute fabric; and controller configured to control the of compute tiles. Each compute tiles includes, in part, a multitude of multiplying bit-cells (MBC) disposed along M rows and N columns, where M an N are integers greater than one. Each MBC is configured to: multiply a first bit by a second bit to generate a multiplication value; convert the multiplication value to a charge; and store the charge in a capacitor disposed in the MBC.

Abstract: An apparatus for receiving signals includes a low noise amplifier (LNA) configured to receive a radio frequency (RF) signal. An I/Q direct down converter is coupled to the LNA. The I/Q direct down converter is configured to split the RF signal into real and imaginary components and to down convert the real and imaginary components directly to baseband signals. A local oscillator (LO) is coupled to the I/Q direct down converter and is configured to drive the I/Q direct down converter. First and second filters are coupled to the I/Q direct down converter. The first and second filters are configured to filter the down converted real and imaginary components, respectively. First and second analog-to-digital converters (ADCs) are coupled to the first and second filters, respectively. The first and second ADCs are configured to convert the real and imaginary components into digital signals.

Abstract: The invention provides a unique apparatus and method which varies the capacitance coupled to a circuit. In one embodiment, the variable capacitance comprises a unique variable capacitance array with multiple capacitance modules which can be selectively enabled. Each capacitance module has a capacitive value and a corresponding parasitic capacitance. The invention provides high linearity, low spread, improves the response to power fluctuations by maintaining a consistent relationship between the capacitive value and the parasitic capacitance in each capacitance module. For example, the invention can be used with devices to provide a linear variation of capacitance. In addition, the invention can be used to calibrate a wide range of devices.