Patents by Inventor Jorge Agraz-Guerena

Jorge Agraz-Guerena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide
    Patent number: 4278705
    Abstract: A process for making dielectrically isolated silicon integrated circuits which use silicon oxide filled trenches to provide isolation is described. To minimize damage to the silicon, the trenches are filled by sequentially annealed oxidation process which involves alternately growing some oxide and then annealing to relieve stresses before growing more oxide.
    Type: Grant
    Filed: November 8, 1979
    Date of Patent: July 14, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Jorge Agraz-Guerena, Lewis E. Katz, Bernard L. Morris
  • Integrated circuit and method for fabrication thereof
    Patent number: 4199775
    Abstract: An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.
    Type: Grant
    Filed: September 3, 1974
    Date of Patent: April 22, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Jorge Agraz-Guerena, Alan W. Fulton
  • Method for fabrication of improved bipolar injection logic circuit
    Patent number: 4076556
    Abstract: An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.
    Type: Grant
    Filed: June 1, 1976
    Date of Patent: February 28, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Jorge Agraz-Guerena, Alan William Fulton