Patents by Inventor Jorge Campello

Jorge Campello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7233903
    Abstract: Methods and/or systems/apparatus using speech for marking and subsequently identifying one or more items having electronically-readable identifiers respectively marked thereon comprise the following steps and/or perform the following operations. First, at least a portion of the electronically-readable identifier marked on an item is inputted. A user then inputs a spoken utterance that corresponds to the item. Next, the electronically-readable identifier inputted from the item is associated with the spoken utterance input from the user. Thus, when the electronically-readable identifier is inputted a next time, the spoken utterance associated with the electronically-readable identifier may be outputted. The present invention may also be embodied as an article of manufacture comprising a machine readable medium containing one or more programs which when executed implement the steps/operations of the invention.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: June 19, 2007
    Assignee: International Business Machines Corporation
    Inventors: Thiruvilwamalai Venkatraman Raman, Jorge Campello de Souza, Bruce Alexander Wilson, Jeffrey Alan Kusnitz
  • Publication number: 20070033426
    Abstract: A chipset in a host computer enables the internal HDD of the host computer to be accessed by another computer either through the USB port (for direct access shared storage) or the Ethernet port (for network attached storage) without having to boot the host computer.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Bruce Wilson, Jorge Campello, Richard New
  • Patent number: 7113555
    Abstract: A data channel includes a data detector that approximates both inter-symbol-interference (ISI) and random timing perturbations using a single finite-state hidden Markov model. The ISI is approximated by a finite impulse response and the timing perturbations are approximated by a first order random walk. The data signal, which is subject to inter-symbol interference and timing perturbations, is sampled periodically over a succession of time epochs without regard to timing perturbations. Timing perturbation values and data states are then assigned for each epoch, and each timing perturbation value is paired with each data state to arrive at a set of composite states. Probabilities are then assigned between composite states in successive epochs to arrive at the most probable composite state sequence corresponding to the sequence of detected data values from the sampled data. A Viterbi algorithm is then applied to find the maximum likelihood sequence of composite states.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 26, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jorge Campello de Souza, Brian H. Marcus, Richard M. H. New, Bruce A. Wilson
  • Patent number: 7076625
    Abstract: A multimedia storage device such as a hard disk drive has an unrestricted area that is accessible to client devices outside the device such that digital multimedia stored on the unrestricted area may be accessed by the client devices. Also, the device has a restricted area containing digital multimedia that is at all times inaccessible to the client devices. However, the digital multimedia in the restricted area is accessible only by a controller in the device that always and under all circumstances converts the digital multimedia in the restricted area to analog format prior to permitting a client device to access content embodied by the multimedia.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 11, 2006
    Assignee: Hitachi Global Storage Technologies
    Inventor: Jorge Campello de Souza
  • Publication number: 20060136776
    Abstract: Embodiments of the present invention provide a method and a system for monitoring a storage device for usage and warranty. In one embodiment, a data storage apparatus comprises a nonvolatile storage; and a data storage controller configured to store a log of status parameters of the data storage apparatus in the nonvolatile storage. The log of status parameters of the data storage apparatus in the nonvolatile storage is not resettable. Storing of the log of status parameters of the data storage apparatus in the nonvolatile storage cannot be disabled.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 22, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Jorge Campello, Bruce Wilson, Richard New
  • Publication number: 20060122854
    Abstract: Embodiments of the present invention provide a system and a method for generating warranty and pricing information for one or more data storage apparatuses. In one embodiment, a system for processing status parameters of one or more data storage apparatuses comprises at least one host system configured to retrieve one or more status parameters of one or more data storage apparatus; a vendor system; and a network coupled with the at least one host system and the vendor system. The at least one host system is configured to send the one or more status parameters via the network to the vendor system. The vendor system is configured to use the one or more status parameters to generate any one or more of warranty information, pricing information, and design improvement information for the data storage apparatus.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 8, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Jorge Campello, Bruce Wilson, Richard New
  • Publication number: 20060080501
    Abstract: A mobile computing hard disk drive has both a flash memory device and a DRAM device, with the HDD controller managing data storage between disk, DRAM, and flash both when write requests arrive and when the HDD is idle to optimize flash memory device life and system performance.
    Type: Application
    Filed: October 12, 2004
    Publication date: April 13, 2006
    Inventors: Daniel Auerbach, Jorge Campello, Frank Chu, Spencer Ng
  • Publication number: 20060026431
    Abstract: Digital watermark data is embedded into compressed media content that is transmarked when the compressed media content is converted to an analog format or into an uncompressed digital format. The watermark data uniquely identifies the converter/player device/user that converted the watermark-protected digital media content into the analog format or the uncompressed digital format. The presented media content in the analog format or the uncompressed digital format is modified as a function of the watermark data and the digital signature obtained from the converter/player device/user. The modifications are visible and essentially produce a correspondingly different media presentation for each converter/player device/user. The modifications, however, are selected so that they are nonessential to the storyline and, consequently, not noticed by a casual user.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Applicant: Hitachi Global Storage Technologies B.V.
    Inventor: Jorge Campello De Souza
  • Patent number: 6789227
    Abstract: A computer-implemented system and method is for generating low-density parity check (LDPC) codes. One aspect of the invention includes a method for generating high rate LDPC codes that first constructs a matrix (H) of size m×n having m rows of check nodes and n columns of bit nodes. The matrix meets the following requirements: the weight of the j−th column equals aj; each row, r, has weight at most br; and the matrix H can be represented by a Tanner graph that has a girth of at least g≧g. The method then iteratively adds an (n+1)th column (U1) to matrix H, wherein the size of U1, is initially empty and is at most an+1, and wherein U1, comprises a set of i check nodes such that i is greater than or equal to 0 and i is less than an+1. The method then iteratively adds check nodes to U1. such that each check node does not violate predetermined girth and check-degree constraints. The matrix H is updated when a new column is added.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jorge Campello De Souza, Dharmendra Shantilal Modha, Sridhar Rajagopalan
  • Publication number: 20040071232
    Abstract: A data channel includes a data detector that approximates both inter-symbol-interference (ISI) and random timing perturbations using a single finite-state hidden Markov model. The ISI is approximated by a finite impulse response and the timing perturbations are approximated by a first order random walk. The data signal, which is subject to inter-symbol interference and timing perturbations, is sampled periodically over a succession of time epochs without regard to timing perturbations. Timing perturbation values and data states are then assigned for each epoch, and each timing perturbation value is paired with each data state to arrive at a set of composite states. Probabilities are then assigned between composite states in successive epochs to arrive at the most probable composite state sequence corresponding to the sequence of detected data values from the sampled data. A Viterbi algorithm is then applied to find the maximum likelihood sequence of composite states.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Inventors: Jorge Campello de Souza, Brian H. Marcus, Richard M. H. New, Bruce A. Wilson
  • Patent number: 6708308
    Abstract: This invention is a Viterbi algorithm combined with the use of error filters outputs to produce bit reliabilities. The present invention is a SOVA-like method using error filters to reduce the complexity of bit reliability determination further than that of the ordinary SOVA method. Error patterns corresponding to each of a handful of dominant i.e., most common error patterns are determined from experimental data. Error filters determine likelihoods of each postulated error pattern. These likelihoods are then combined to produce bit reliabilities that may be passed on to an outer error correction decoder. The filters, typically six or seven of them, resolve most of the errors thereby simplifying computation dramatically.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jorge Campello De Souza, Brian H. Marcus, Richard M. H. New, Bruce A. Wilson
  • Publication number: 20030014718
    Abstract: A computer-implemented system and method is for generating low-density parity check (LDPC) codes. One aspect of the invention includes a method for generating high rate LDPC codes that first constructs a matrix (H) of size m×n having m rows of check nodes and n columns of bit nodes. The matrix meets the following requirements: the weight of the j−th column equals aj; each row, r, has weight at most br; and the matrix H can be represented by a Tanner graph that has a girth of at least g≧g. The method then iteratively adds an (n+1)th column (U1) to matrix H, wherein the size of U1, is initially empty and is at most an+1, and wherein U1, comprises a set of i check nodes such that i is greater than or equal to 0 and i is less than an+1. The method then iteratively adds check nodes to U1. such that each check node does not violate predetermined girth and check-degree constraints. The matrix H is updated when a new column is added.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 16, 2003
    Applicant: International Business Machines Corporation
    Inventors: Jorge Campello De Souza, Dharmendra Shantilal Modha, Sridhar Rajagopalan
  • Publication number: 20020138273
    Abstract: Methods and/or systems/apparatus using speech for marking and subsequently identifying one or more items having electronically-readable identifiers respectively marked thereon comprise the following steps and/or perform the following operations. First, at least a portion of the electronically-readable identifier marked on an item is inputted. A user then inputs a spoken utterance that corresponds to the item. Next, the electronically-readable identifier inputted from the item is associated with the spoken utterance input from the user. Thus, when the electronically-readable identifier is inputted a next time, the spoken utterance associated with the electronically-readable identifier may be outputted. The present invention may also be embodied as an article of manufacture comprising a machine readable medium containing one or more programs which when executed implement the steps/operations of the invention.
    Type: Application
    Filed: March 26, 2001
    Publication date: September 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: Thiruvilwamalai Venkatraman Raman, Jorge Campello de Souza, Bruce Alexander Wilson, Jeffrey Alan Kusnitz
  • Publication number: 20020129318
    Abstract: This invention is a Viterbi algorithm combined with the use of error filters outputs to produce bit reliabilities. The present invention is a SOVA-like method using error filters to reduce the complexity of bit reliability determination further than that of the ordinary SOVA method. Error patterns corresponding to each of a handful of dominant i.e., most common error patterns are determined from experimental data. Error filters determine likelihoods of each postulated error pattern. These likelihoods are then combined to produce bit reliabilities that may be passed on to an outer error correction decoder. The filters, typically six or seven of them, resolve most of the errors thereby simplifying computation dramatically.
    Type: Application
    Filed: January 10, 2001
    Publication date: September 12, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jorge Campello De Souza, Brian H. Marcus, Richard M.H. New, Bruce A. Wilson