Abstract: A method for record access in a distributed system includes receiving a request for a record, wherein the request comprises a transmitted key and a record identifier, extracting a location identifier and a transmitted pseudorandom portion from the transmitted key, obtaining a stored pseudorandom portion from a location in a key memory specified by the location identifier, and providing access to the record identified by the record identifier when the transmitted pseudorandom portion matches the stored pseudorandom portion.

Abstract: A method for record access in a distributed system includes receiving a request for a record, wherein the request comprises a transmitted key and a record identifier, extracting a location identifier and a transmitted pseudorandom portion from the transmitted key, obtaining a stored pseudorandom portion from a location in a key memory specified by the location identifier, and providing access to the record identified by the record identifier when the transmitted pseudorandom portion matches the stored pseudorandom portion.

Abstract: An apparatus includes a server comprising n operating system images and an IOV aware root complex; a plurality of physical I/O devices comprising n virtual I/O functions; and a PCI Express bus operatively connected to the server and the plurality physical I/O devices via the root complex, wherein the root complex is operable to provide communication between the n operating system images and the n virtual I/O function, and wherein the server and the plurality of physical I/O devices are modules in a chassis.

Abstract: A blade server includes a chassis; a first plurality of bays in the chassis, wherein the first plurality of bays is adapted to receive and at least partially house a plurality of CPU modules, and wherein the first plurality of bays is accessible through a first side of the chassis; a second plurality of bays in the chassis, wherein the second plurality of bays is adapted to receive and at least partially house a plurality of PCI-Express modules, and wherein the second plurality of bays is accessible through a second side of the chassis; and a midplane board arranged to pass a PCI-Express signal between at least one of the plurality of CPU modules and at least one of the plurality of PCI-Express modules.

Abstract: A “firewall” apparatus is placed between a single bus master device and a multimaster I2C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and isolates the single bus master from the multimaster bus. Therefore the single bus master needs only to retry transactions that receive unexpected NAKs and all complex multimaster issues, such as bus collisions, transaction termination and bus recovery, associated with the actual error that occurred on the multimaster bus are handled by the firewall apparatus. In accordance with one embodiment, when the single bus master attempts to launch a transaction at a time when the multimaster I2C bus is busy, the firewall apparatus absorbs the address driven by the single bus master and then stalls the transaction until the firewall apparatus is able to successfully acquire and drive the address on the multimaster bus. The firewall apparatus is implemented in a preferred embodiment by a programmed microcontroller.

Abstract: A hot plugging system has a first mechanism for selectively connecting, responsive to a first control signal, each of a plurality of slots with a primary bus, e.g.,a PCI bus connected to a system bus of a computer system; and a second mechanism for connecting, responsive to a second control signal, at least one of the slots with a secondary bus, e.g., a dedicated PCI bus, or other connection interface, used for testing purposes during hot-plug insertion of an adapter card. In another aspect, a hot plug controller makes the connection of the at least one slot to the primary bus in response to a BUS_IDLE signal from the host bridge that indicates when the PCI bus is idle. The BUS_IDLE signal can be generated from the FRAME and IRDY signals for the primary bus by combinational logic in the host bridge. In this way, the hot plug controller need not be connected to and load the shared lines, e.g., the FRAME and IRDY lines, of that bus.

Abstract: A digital data transfer system comprises a source module and a destination module interconnected by an information transfer medium. The source module initiates a transfer operation in which it transfers a data item and an associated address over an information transfer medium. The address having an aperture identification portion that identifies one of a plurality of apertures. The destination module receives the data item and the associated address from the information transfer medium during the transfer operation, the destination module using the one of the plurality of apertures identified by the aperture identification portion to generate an aperture value for association with the data item. The source module can also initiate a retrieval operation, during which it transfers an address over the information transfer medium to retrieve previously transferred information.

Abstract: A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor.

Abstract: A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain.