Abstract: A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Abstract: A system for performing cycle accurate simulation of a circuit design can include a plurality of cycle accurate models, wherein each cycle accurate model is a software object representation of a hardware function, and a scheduler configured to execute each cycle accurate model at clock cycle boundaries determined during a simulation session.

Abstract: Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design block, with the first bus being an interface bus of a processor. An interface description is determined for a bus functional model of the interface bus of the processor. The interface description includes a synchronization bus for coordinating the bus functional model and a hardware description language (HDL) testbench. A hardware specification is generated that couples the first bus of the design block with the interface description, and couples the HDL testbench with the second bus of the design block and with the synchronization bus of the interface description. The simulation for verifying the design block is automatically generated from the bus functional model and the hardware specification.

Abstract: A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.

Abstract: A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.

Abstract: Various approaches for simulating a circuit design are disclosed. In one approach, a first specification of a testbench and a second specification of the circuit design are generated in a hardware description language. The circuit design is synchronous to at least one clock signal. The second specification of the circuit design is automatically translated into a third specification in a general-purpose programming language, and the third specification specifies the behavior of the circuit design at transitions of the at least one clock signal. A fourth specification of an interface between the first specification of the testbench and the third specification of the circuit design is automatically generated. A first behavior of the circuit design is simulated using the first and third specifications linked by the fourth specification and the stimuli from the test bench.

Abstract: Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.

Abstract: A method is provided for building a simulation environment. A first functional model is produced that emulates the interaction of a processor with a first interface of a bus for the processor as controlled by a first script. A second functional model is produced that is controllable to emulate multiple interfaces. The second functional model is controlled to emulate a second interface of an input/output peripheral by a second script. A third functional model is produced that emulates a memory subsystem. A simulation environment is automatically generated that simulates the design block for a programmable logic device. The simulation environment couples the bus to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between transactions of the first and second scripts.

Abstract: A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.

Abstract: Methods and structures for efficiently implementing an accumulator-based load-store CPU architecture in a programmable logic device (PLD). The PLD includes programmable logic blocks, each logic block including function generators that can be optionally programmed to function as lookup tables or as RAM blocks. Each element of the CPU is implemented using these logic blocks, including an instruction register, an accumulator pointer, a register file, and an operation block. The register file is implemented using function generators configured as RAM blocks. This implementation eliminates the need for time-consuming accesses to an off-chip register file or to a dedicated RAM block.