Abstract: A method and apparatus are described for OTP control logic with randomization for sensing and writing fuse values. In an embodiment, OTP control logic has an address counter to determine an address of a fuse to be read from an OTP fuse box and a corresponding address of a shadow register, a fuse box addressing circuit to read a fuse value from a fuse of the fuse box, a clock circuit coupled to the address counter to provide a clock signal to the address counter, and a randomization circuit to interrupt the clock signal at random times to prevent the address counter from determining a next address in response to the clock signal.

Abstract: The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.

Abstract: The invention relates to a random clock generator comprising an input receiving a master clock signal MCIk, and a clock signal reduction circuit (101) receiving the master clock signal MCIk and a whole number N and supplying an output signal corresponding to a train of N pulses every M clock pulse, M being a whole number higher than 1 and N being a whole number higher than 1 and lower than or equal to M. A number generator (102) and (103) supplies a new number (N) to the clock signal reduction circuit every P pulse of a master clock signal, N and/or P being produced randomly.