Patents by Inventor Jorge Garcia Pabon

Jorge Garcia Pabon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11640693
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Publication number: 20220414967
    Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Jorge Garcia Pabon, John Gierach
  • Publication number: 20220383569
    Abstract: Methods, systems and apparatuses may provide for technology that selects a location of a pixel block based on a location of a graphics polygon, wherein the pixel block contains the graphics polygon. The technology may also convert the graphics polygon into a pixel-based representation within the pixel block during a single transaction.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Jorge Garcia Pabon, Subramaniam Maiyuran, Raghavendra Kamath Miyar, Vamsee Vardhan Chivukula, Krishan Malik, Abhishek Varshney
  • Publication number: 20220148261
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Patent number: 11176736
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Publication number: 20210217235
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 15, 2021
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Patent number: 10916052
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Publication number: 20200342662
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Patent number: 10628910
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
  • Publication number: 20200098078
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
  • Patent number: 10430990
    Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge Garcia Pabon, Vasanth Ranganathan, Saikat Mandal, Karol Szerszen, Luis Cruz Camacho, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20190087999
    Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge Garcia Pabon, Vasanth Ranganathan, Saikat Mandal, Karol Szerszen, Luis Cruz Camacho, Abhishek R. Appu, Joydeep Ray