Patents by Inventor Jorge Garcia Pabon
Jorge Garcia Pabon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11640693Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: GrantFiled: November 15, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Publication number: 20220414967Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Prasoonkumar Surti, Jorge Garcia Pabon, John Gierach
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Publication number: 20220383569Abstract: Methods, systems and apparatuses may provide for technology that selects a location of a pixel block based on a location of a graphics polygon, wherein the pixel block contains the graphics polygon. The technology may also convert the graphics polygon into a pixel-based representation within the pixel block during a single transaction.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Jorge Garcia Pabon, Subramaniam Maiyuran, Raghavendra Kamath Miyar, Vamsee Vardhan Chivukula, Krishan Malik, Abhishek Varshney
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Publication number: 20220148261Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: ApplicationFiled: November 15, 2021Publication date: May 12, 2022Applicant: Intel CorporationInventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Patent number: 11176736Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: GrantFiled: January 21, 2021Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Publication number: 20210217235Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: ApplicationFiled: January 21, 2021Publication date: July 15, 2021Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Patent number: 10916052Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: GrantFiled: April 26, 2019Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Publication number: 20200342662Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.Type: ApplicationFiled: April 26, 2019Publication date: October 29, 2020Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
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Patent number: 10628910Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.Type: GrantFiled: September 24, 2018Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
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Publication number: 20200098078Abstract: An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 24, 2018Publication date: March 26, 2020Applicant: Intel CorporationInventors: Tomasz Bujewski, Radoslaw Drabinski, Subramaniam Maiyuran, Jorge Garcia Pabon, Raghavendra Miyar, Rajarshi Bajpayee
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Patent number: 10430990Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.Type: GrantFiled: September 20, 2017Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Subramaniam Maiyuran, Jorge Garcia Pabon, Vasanth Ranganathan, Saikat Mandal, Karol Szerszen, Luis Cruz Camacho, Abhishek R. Appu, Joydeep Ray
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Publication number: 20190087999Abstract: An apparatus to facilitate pixel compression is disclosed. The apparatus includes a rasterizer module to convert an image to a plurality of pixels, an interface coupled to the rasterizer module, a depth check module coupled to the interface and compression logic to perform a compression encoding on the plurality of pixels, including dividing the plurality of pixels into a mega pixel block having a plurality of pixel blocks, determining coverage information for pixels in each of the plurality of pixel blocks, encoding each of the plurality of pixel blocks based on the coverage information to generate a mega encoded block.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Applicant: Intel CorporationInventors: Subramaniam Maiyuran, Jorge Garcia Pabon, Vasanth Ranganathan, Saikat Mandal, Karol Szerszen, Luis Cruz Camacho, Abhishek R. Appu, Joydeep Ray