Patents by Inventor Jorge Hermosillo

Jorge Hermosillo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Offloading MAC/link layer functions
    Patent number: 10531382
    Abstract: A wireless device having processor circuitry; and a hardware circuit configured to implement, during an active steady-state of a Medium Access Control/Link Layer (MAC/LL) with scheduled channel access, a MAC/LL function without processor circuitry intervention, wherein the steady-state is a state that is control packet transmission free for managed connections in connection oriented communications or a continuous broadcast or scan operation in connectionless communications.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: David Arditti Ilitzky, Jorge Hermosillo, Jorge Carballido Gamio, Arturo Veloz, Venkatesh Rajendran, Jorge Romero Aragon, Carlos A. Flores Fajardo, Rodrigo Varela Leos, Bernard Deadman
  • OFFLOADING MAC/LINK LAYER FUNCTIONS
    Publication number: 20180368192
    Abstract: A wireless device having processor circuitry; and a hardware circuit configured to implement, during an active steady-state of a Medium Access Control/Link Layer (MAC/LL) with scheduled channel access, a MAC/LL function without processor circuitry intervention, wherein the steady-state is a state that is control packet transmission free for managed connections in connection oriented communications or a continuous broadcast or scan operation in connectionless communications.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: David Arditti Ilitzky, Jorge Hermosillo, Jorge Carballido Gamio, Arturo Veloz, Venkatesh Rajendran, Jorge Romero Aragon, Carlos A. Flores Fajardo, Rodrigo Varela Leos, Bernard Deadman
  • Hardware-efficient on-chip calibration of analog/RF through sub-sampling
    Patent number: 9194911
    Abstract: A digital on-die-test engine (OTE) generates stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: November 24, 2015
    Assignee: iNTEL CORPORATION
    Inventors: Georgios Palaskas, Jorge Hermosillo, Marian K. Verhelst
  • HARDWARE-EFFICIENT ON-CHIP CALIBRATION OF ANALOG/RF THROUGH SUB-SAMPLING
    Publication number: 20130173203
    Abstract: A digital on-die-test engine (OTE) is disclosed to generate stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 4, 2013
    Inventors: GEORGIOS PALASKAS, Jorge Hermosillo, Marian K. Verhelst