Abstract: A bonding structure for a semiconductor substrate and related method are provided. The bonding structure includes a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure. The second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. The bonding structure can be used to bond chips to wafer or wafer to wafer and provides a greater bond strength than just a thick oxide layer.

Abstract: A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

Abstract: A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

Abstract: Photonic integrated circuit (PIC) packages include a PIC die. The PIC die includes a waveguide(s) positioned on the PIC die, and a groove(s) formed in a surface of the PIC die. The groove(s) corresponds to and is positioned directly adjacent the waveguide(s). The PIC package also includes an optical fiber(s) operatively coupled to the waveguide(s) of the PIC die. The optical fiber(s) are positioned in the groove(s) of the PIC die and include an end positioned adjacent the waveguide(s). Additionally, the PIC package includes a plate positioned over a section of the optical fiber(s), and the plate includes a first edge positioned adjacent the waveguide(s) of the PIC die, and a second edge positioned opposite the first edge. The PIC package also includes a first adhesive disposed along the second edge of the plate and a second adhesive disposed along the first edge of the plate.

Abstract: The present disclosure relates to stacked semiconductor devices and, more particularly, to stacked integrated circuit (IC) chips or wafers and to their methods of manufacturing. The stacked semiconductor device of the present disclosure comprises a first chip having a surface, a hydrogen permeable barrier layer on the surface of the first chip, and a second chip bonded to the first chip. The hydrogen permeable barrier layer is positioned between the first chip and the second chip.

Abstract: An optical system includes a photonics chip, a bridge waveguide structure formed on the chip, and an optical fiber disposed over the chip and optically aligned with the bridge waveguide structure. A cavity between the bridge waveguide structure and the chip is at least partially filled with an adhesive resin and a filler material having a coefficient of thermal expansion (CTE) less than that of the adhesive resin. The filler material may include filler particles dispersed throughout the adhesive resin, or a discrete layer of material separate from the adhesive resin. The composite adhesive material filling the cavity has an effective coefficient of thermal expansion less than the coefficient of thermal expansion of conventional adhesive resins. This lower effective CTE improves the survivability of the overlying bridge waveguide structure following thermal cycling of the optical system.

Abstract: An optical system includes a photonics chip, a bridge waveguide structure formed on the chip, and an optical fiber disposed over the chip and optically aligned with the bridge waveguide structure. A cavity between the bridge waveguide structure and the chip is at least partially filled with an adhesive resin and a filler material having a coefficient of thermal expansion (CTE) less than that of the adhesive resin. The filler material may include filler particles dispersed throughout the adhesive resin, or a discrete layer of material separate from the adhesive resin. The composite adhesive material filling the cavity has an effective coefficient of thermal expansion less than the coefficient of thermal expansion of conventional adhesive resins. This lower effective CTE improves the survivability of the overlying bridge waveguide structure following thermal cycling of the optical system.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the front side, the integrated circuit structure comprising: a through-silicon-via (TSV) at least partially within a dielectric layer extending away from the front side; a first metal adjacent to the TSV and within the dielectric layer, the first metal being substantially surrounded by a first seed layer; a conductive pad over the first metal and the TSV and extending away from the front side, wherein the conductive pad provides electrical connection between the TSV and the first metal and includes a second seed layer substantially surrounding a second metal, wherein the second seed layer separates the second metal from the first metal and the TSV.

Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

Abstract: A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.

Abstract: A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.

Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

Abstract: A method of forming a ruthenium-containing film in a vapor deposition process, including depositing ruthenium with an assistive metal species that increases the rate and extent of ruthenium deposition in relation to deposition of ruthenium in the absence of such assistive metal species. An illustrative precursor composition useful for carrying out such method includes a ruthenium precursor and a strontium precursor in a solvent medium, wherein one of the ruthenium and strontium precursors includes a pendant functionality that coordinates with the central metal atom of the other precursor, so that ruthenium and strontium co-deposit with one another. The method permits incubation time for ruthenium deposition on non-metallic substrates to be very short, thereby accommodating very rapid film formation in processes such as atomic layer deposition.

Abstract: A layered heterostructure field effect transistor (HFET) comprises a substrate, a first semiconductor oxide layer grown on the substrate, and a second semiconductor oxide layer grown on the first layer semiconductor layer and having an energy band gap different from that of the first semiconductor layer, and the second layer also having a gate region and a drain region and a source region with electrical contacts to gate, drain and source regions sufficient to form a HFET. The substrate may be a material, including a single crystal material, and may contain a buffer layer material on which the first semiconductor layer is grown. The conductivity type of the first and second semiconductor layers and the composition of the semiconductor oxide layers can be selected to improve performance for desired operational features of the HFET. This layered structure can be applied for the improvement in the function and high frequency and high power performance of semiconductor HFET devices.

Abstract: A method of forming a ruthenium-containing film in a vapor deposition process, including depositing ruthenium with an assistive metal species that increases the rate and extent of ruthenium deposition in relation to deposition of ruthenium in the absence of such assistive metal species. An illustrative precursor composition useful for carrying out such method includes a ruthenium precursor and a strontium precursor in a solvent medium, wherein one of the ruthenium and strontium precursors includes a pendant functionality that coordinates with the central metal atom of the other precursor, so that ruthenium and strontium co-deposit with one another. The method permits incubation time for ruthenium deposition on non- metallic substrates to be very short, thereby accommodating very rapid film formation in processes such as atomic layer deposition.

Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.

Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.

Abstract: A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/?0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/?0.225.