Patents by Inventor Jorge M. Marcial

Jorge M. Marcial has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low noise high thermal conductivity mixed signal package
    Patent number: 8207021
    Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 26, 2012
    Assignee: Raytheon Company
    Inventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
  • LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE
    Publication number: 20120015485
    Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: Raytheon Company
    Inventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
  • Low noise high thermal conductivity mixed signal package
    Patent number: 8067833
    Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: November 29, 2011
    Assignee: Raytheon Company
    Inventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
  • LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE
    Publication number: 20110018126
    Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.
    Type: Application
    Filed: July 23, 2009
    Publication date: January 27, 2011
    Applicant: Raytheon Company
    Inventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper