Patents by Inventor Jorge Munoz
Jorge Munoz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130049079Abstract: According to an exemplary embodiment, a small-outline package includes a power transistor having a source and a drain, the power transistor situated on a paddle of a leadframe of the small-outline package. The source of the power transistor is electrically connected to a plurality of source leads. The drain of the power transistor is electrically and thermally connected to a top side of the paddle of the leadframe, the paddle of the leadframe being exposed from a bottom surface of the small-outline package, thereby providing a direct electrical contact to the drain from a bottom side of the paddle of the leadframe.Type: ApplicationFiled: July 25, 2012Publication date: February 28, 2013Applicant: INTERNATIONAL RECTIFIER CORPORATIONInventor: Jorge Munoz
-
Patent number: 7682421Abstract: A liquid is degassed with an apparatus including a membrane contactor, where the liquid is drawn through the apparatus by gravity.Type: GrantFiled: October 12, 2006Date of Patent: March 23, 2010Assignee: Celgard LLCInventors: Gareth P. Taylor, Jorge Munoz
-
Publication number: 20080087164Abstract: A liquid is degassed with an apparatus including a membrane contactor, where the liquid is drawn through the apparatus by gravity.Type: ApplicationFiled: October 12, 2006Publication date: April 17, 2008Inventors: Gareth P. Taylor, Jorge Munoz
-
Patent number: 6984890Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.Type: GrantFiled: July 2, 2004Date of Patent: January 10, 2006Assignee: International Rectifier CorporationInventors: Bharat Shivkumar, Daniel M. Kinzer, Jorge Munoz
-
Publication number: 20040238971Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.Type: ApplicationFiled: July 2, 2004Publication date: December 2, 2004Applicant: International Rectifier CorporationInventors: Bharat Shivkumar, Daniel M. Kinzer, Jorge Munoz
-
Patent number: 6776399Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.Type: GrantFiled: May 20, 2002Date of Patent: August 17, 2004Assignee: International Rectifier CorporationInventors: Bharat Shivkumar, Daniel M. Kinzer, Jorge Munoz
-
Publication number: 20020135079Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.Type: ApplicationFiled: May 20, 2002Publication date: September 26, 2002Applicant: International Rectifier CorporationInventors: Bharat Shivkumar, Daniel M. Kinzer, Jorge Munoz
-
Patent number: 6410989Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.Type: GrantFiled: January 4, 1999Date of Patent: June 25, 2002Assignee: International Rectifier CorporationInventors: Bharat Shivkumar, Daniel M. Kinzer, Jorge Munoz
-
Patent number: 6396127Abstract: A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection, the copper plate including at least one chamfered edge extending upward and away from the first metalized region; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.Type: GrantFiled: January 3, 2000Date of Patent: May 28, 2002Assignee: International Rectifier CorporationInventors: Jorge Munoz, Rod DeLeon
-
Patent number: 6376910Abstract: A solderable back contact for semiconductor die consists of a titanium layer bonded to the bottom of the die. The free surface of the titanium layer is coated with a copper layer. A soft solder layer joins the bottom of the die to a copper lead frame by first heating the die to below the melting point of the solder, and then ultrasonically “scrubbing” the solder to cause it to bond to the die and lead frame with a minimum sized solder fillet.Type: GrantFiled: June 23, 1999Date of Patent: April 23, 2002Assignee: International Rectifier CorporationInventors: Jorge Munoz, Chuan Cheah
-
Patent number: 6040626Abstract: A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.Type: GrantFiled: January 4, 1999Date of Patent: March 21, 2000Assignee: International Rectifier Corp.Inventors: Chuan Cheah, Jorge Munoz, Dan Kinzer
-
Patent number: 5887776Abstract: A portable radio-cassette adapter plate which is secured to a portable radio. An offset belt clip is secured to the portable radio-cassette adapter plate by an offset belt clip tether which is adjustable in length. By clamping the offset belt clip to a waistband or belt of a user, the portable radio is suspended comfortably by the offset belt clip tether. The distance which the portable radio is suspended below the waistband or belt of the user may be varied for comfort according to personal preference.Type: GrantFiled: October 8, 1996Date of Patent: March 30, 1999Inventor: Jorge Munoz