Patents by Inventor Jorge Salcedo

Jorge Salcedo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180211210
    Abstract: The computer implemented method and computer program product provided in accordance with the present invention allows a user-company to consign and track corporate personal protective equipment, or “PPE,” assets to specific employees, suppliers, contractors, visitors, guests, and other authorized persons, as well as to control, manage, and validate the expiration period of PPE, and the entry and exit of PPE at any job sites and/or industrial and mining operations. The computer implemented method and computer program product use radio frequency identification, or “RFID,” technology via fixed control or mobile/portable control methodologies.
    Type: Application
    Filed: March 22, 2018
    Publication date: July 26, 2018
    Inventor: Jorge Salcedo
  • Publication number: 20150248635
    Abstract: The computer implemented method and computer program product provided in accordance with the present invention allows a user-company to consign and track corporate personal protective equipment, or “PPE,” assets to specific employees, suppliers, contractors, visitors, guests and other authorized persons, as well as to control, manage and validate the expiration period of PPE, and the entry and exit of PPE at any job sites and/or industrial and mining operations. The computer implemented method and computer program product use radio frequency identification, or “RFID,” technology via fixed control or mobile/portable control methodologies.
    Type: Application
    Filed: August 22, 2013
    Publication date: September 3, 2015
    Inventor: Jorge Salcedo
  • Patent number: 7167350
    Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: January 23, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jorge Salcedo-Suner, Charvaka Duvvury, Roger A. Cline, Jose A. Cadena-Hernandez
  • Publication number: 20050104154
    Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.
    Type: Application
    Filed: November 3, 2004
    Publication date: May 19, 2005
    Inventors: Jorge Salcedo-Suner, Charvaka Duvvury, Roger Cline, Jose Cadena-Hernandez
  • Patent number: 6636067
    Abstract: A reliable method of testing a CMOS-based integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up. The test method detects a low impedance path between the integrated circuit device I/O pin(s) and GND(s) caused by a parasitic SCR that is not detectable using conventional latch-up detection test methods.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: October 21, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Jorge Salcedo-Suner
  • Patent number: D727435
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 21, 2015
    Assignee: Convertidora Industrial, S.A.B., de C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D727436
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 21, 2015
    Assignee: Convertidora Industrial, S.A.B., DE C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D727437
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 21, 2015
    Assignee: Convertidora Industrial, S.A.B., DE C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D738960
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 15, 2015
    Assignee: Convertidora Industrial, S.A.B., De C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D738961
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 15, 2015
    Assignee: Convertidora Industrial, S.A.B., DE C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D739472
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 22, 2015
    Assignee: Convertidora Industrial, S.A.B., DE C.V.
    Inventor: Jorge Salcedo Padilla
  • Patent number: D739473
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: September 22, 2015
    Assignee: Convertidora Industrial, S.A.B., DE C.V.
    Inventor: Jorge Salcedo Padilla