Patents by Inventor JORGE ULISES MARTINEZ ARAIZA

JORGE ULISES MARTINEZ ARAIZA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220004342
    Abstract: An embodiment of an electronic apparatus may include a substrate and a controller coupled to the substrate, the controller including circuitry to control access to a NAND-based storage media that includes a plurality of NAND devices located on the substrate and organized into two or more physical clusters with each NAND device uniquely assigned to one of the two or more physical clusters, perform data access to a first physical cluster of the two or more physical clusters at a first bandwidth, and perform data access to a second physical cluster of the two or more physical clusters at a second bandwidth that is slower than the first bandwidth. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Applicant: Intel Corporation
    Inventors: Jorge Ulises Martinez Araiza, Michael Leslie Roy, Andrew Morning-Smith
  • Patent number: 10530077
    Abstract: Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity further includes a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Jawad B. Khan, Jorge Ulises Martinez Araiza, Michael D. Nelson
  • Publication number: 20190044259
    Abstract: Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector may include a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity may include first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity may further include a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch may define a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: November 8, 2017
    Publication date: February 7, 2019
    Inventors: JAWAD B. KHAN, JORGE ULISES MARTINEZ ARAIZA, MICHAEL D. NELSON