Abstract: Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.

Abstract: Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.

Abstract: Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: Methods and apparatus are disclosed for battery current monitoring. An example apparatus includes a haptic device, an isolation switch to deliver power from a battery to the haptic device, an integrator to integrate a signal based on a current from the battery to the haptic device to generate an integrator output, and control logic to control the isolation switch based on a comparison of the integrator output to a threshold.

Abstract: Methods and apparatus are disclosed for battery current monitoring. A current controller can prevent injury from a battery operated wearable device. An isolation switch can interrupt delivery of current of a battery to a load in response to an isolation switch control signal to prevent burn injury to a wearer of the battery operated wearable device. The battery operated wearable device can be wrist wearable or head wearable.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus including a first layer having a first coil; a second layer having a second coil, where the first and second coils are stacked relative to each other and configured to be located at an aperture of a housing member including electrically conductive material; and a third layer located under the second layer. The third layer includes a ferrite member located under the second coil such that the second coil is between the first coil and the ferrite member. The first coil or the second coil has a substantially “8” shape.

Abstract: Methods and apparatus are disclosed for battery current monitoring. A current controller can prevent injury from a battery operated wearable device. An isolation switch can interrupt delivery of current of a battery to a load in response to an isolation switch control signal to prevent burn injury to a wearer of the battery operated wearable device. The battery operated wearable device can be wrist wearable or head wearable.

Abstract: Techniques for an electronic device charger are provided. In an example, an apparatus may include a first plurality of interconnects configured to connect with second interconnects of the electronic device, wherein a first interconnect of the first plurality of interconnects is configured to provide charge power to the electronic device, a power transfer circuit configured to receive a supply voltage and to provide the charge power, a first temperature sensor configured to sense a first temperature of one interconnect of the first plurality of interconnects and to provide an indication of the first temperature, and a comparator configured to receive a threshold and the indication of the first temperature and to disable the power transfer circuit if the first temperature violates the threshold.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: An apparatus including a first layer having a first coil; a second layer having a second coil, where the first and second coils are stacked relative to each other and configured to be located at an aperture of a housing member including electrically conductive material; and a third layer located under the second layer. The third layer includes a ferrite member located under the second coil such that the second coil is between the first coil and the ferrite member. The first coil or the second coil has a substantially “8” shape.

Abstract: An apparatus for a multilayer printed circuit board (PCB) coil, comprising: a first coil layer of a PCB; a plurality of vias coupled to and distributed to cover substantially the surface of the first coil layer within the PCB; and a second coil layer of the PCB and coupled to the vias to cover substantially the surface of the second coil layer, wherein the vias are positioned between the first coil layer and the second coil layer and enable substantially high current and low equivalent series resistance (ESR) for the multilayer PCB coil.

Abstract: A method for fabricating an electric coil on a circuit board comprising fabricating on the circuit board a first coil layer comprising a coil trace and a plurality of vias distributed along the length of the coil trace, and overlaying a second coil layer on the first coil layer, wherein the vias of the first coil layer join the first coil layer and the second coil layer.