Patents by Inventor Jorgen STURM

Jorgen STURM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230367733
    Abstract: A method of operating a plurality of driving units for powering electronic units is described. The method includes interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. The method includes applying an ID field for addressing at least one driving unit, and applying a data field comprising information and/or instructions regarding the status of the electronic units. Applying the ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, performing a data length decoding step, and adding a further bit string to the data field including information for carrying out an action by the driving unit.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventors: Kevin BERLIT, Jorgen STURM
  • Publication number: 20230254959
    Abstract: A safety related light system includes: one light source, a first control circuit, and a second control circuit. One of the first control circuit or the second control circuit is selectively enabled to operate in a drive mode to operate the one light source.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 10, 2023
    Inventors: Michael FREY, Jorgen STURM, Thomas FREITAG
  • Patent number: 11102031
    Abstract: The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 24, 2021
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Martin Bölter, Thomas Freitag, Jörgen Sturm, Anton Babushkin
  • Patent number: 10838384
    Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 17, 2020
    Assignee: Melexis Technologies NV
    Inventors: Jörgen Sturm, Michael Bender, Michael Frey, Thomas Freitag
  • Publication number: 20190372803
    Abstract: The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 5, 2019
    Inventors: Martin BÖLTER, Thomas FREITAG, Jörgen STURM, Anton BABUSHKIN
  • Publication number: 20190310597
    Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Jörgen STURM, Michael BENDER, Michael FREY, Thomas FREITAG
  • Patent number: 10368423
    Abstract: A method of operating a plurality of driving units for powering electronic units comprises interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. A step of applying an ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, or allowing each addressed driving unit to decode which action is required by the master control unit, using an R/T command bit, performing a length decoding step, for including information in the ID field regarding the type of instructions included in the data frame, using an F function bit, and assigning data bits to different electronic units or indicating in the length of the bit string in the data field, using a second bit sub-string.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 30, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Jorgen Sturm, Thomas Freitag, Raik Frost, Michael Bender
  • Patent number: 10326583
    Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Jörgen Sturm, Thomas Freitag, Martin Bölter, Anton Babushkin
  • Publication number: 20190132929
    Abstract: A method of operating a plurality of driving units for powering electronic units comprises interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. A step of applying an ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, or allowing each addressed driving unit to decode which action is required by the master control unit, using an R/T command bit, performing a length decoding step, for including information in the ID field regarding the type of instructions included in the data frame, using an F function bit, and assigning data bits to different electronic units or indicating in the length of the bit string in the data field, using a second bit sub-string.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 2, 2019
    Inventors: Jorgen STURM, Thomas FREITAG, Raik FROST, Michael BENDER
  • Publication number: 20180337766
    Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 22, 2018
    Inventors: Jörgen STURM, Thomas FREITAG, Martin BÖLTER, Anton BABUSHKIN