Abstract: A microelectronic device includes a first transistor having a first drain and a first source, a first doped zone constituting one from among the first drain and the first source, a second doped zone constituting the other from among the first drain and the first source, a second transistor comprising a second drain and a second source, a third doped zone constituting the second source or the second drain, a fourth doped zone constituting the other from among the second drain and the second source, a dielectric layer having an upper face in contact with the four doped zones and a rear gate in contact with a lower face of the dielectric layer. The second doped zone and the fourth doped zone form a common electrode.

Abstract: A microelectronic device includes a field-effect n-MOS transistor, a first N-doped zone, constituting one from among the drain and the source of the n-MOS transistor and a second N-doped zone, constituting the other from among the drain and the source of the n-MOS transistor. The device further includes a field-effect p-MOS transistor, a first P-doped zone, constituting one from among the drain and the source of the p-MOS transistor, a dielectric layer in contact with the doped zones and a rear gate. The n-MOS transistor and the p-MOS transistor are separated by a PN junction.

Abstract: A method for producing an FET transistor includes producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; and producing a second gate in the second gate location and against the second side face of the channel.

Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowire

Abstract: Method for producing an FET transistor, comprising: producing a transistor channel, comprising at least one semiconductor nanowire arranged on a substrate and comprising first and second opposite side faces; producing at least two dummy gates, each arranged against one of the first and second side faces of the channel; etching a first of the two dummy gates, forming a first gate location against the first side face of the channel; producing a first gate in the first gate location and against the first side face of the channel; etching a second of the two dummy gates, forming a second gate location against the second side face of the channel; producing a second gate in the second gate location and against the second side face of the channel.

Abstract: A method for programming a one-transistor dynamic memory cell of A2RAM type. The A2RAM memory cell includes a source and a drain doped of a first conductivity type, a body region arranged between the source and the drain, and an insulated gate arranged facing the body region. The body region includes first and second portions extending parallel to the insulated gate, the first portion being doped of a second conductivity type opposite to the first conductivity type and arranged between the insulated gate and the second portion, doped of the first conductivity type. The programming method includes biasing the transistor in an off state by electrical potentials applied to the drain and the gate. The drain potential and the gate potential are chosen in such a way as to create charge carriers by impact ionisation in the second portion.

Abstract: A method for programming a one-transistor dynamic memory cell of A2RAM type. The A2RAM memory cell includes a source and a drain doped of a first conductivity type, a body region arranged between the source and the drain, and an insulated gate arranged facing the body region. The body region includes first and second portions extending parallel to the insulated gate, the first portion being doped of a second conductivity type opposite to the first conductivity type and arranged between the insulated gate and the second portion, doped of the first conductivity type. The programming method includes biasing the transistor in an off state by electrical potentials applied to the drain and the gate. The drain potential and the gate potential are chosen in such a way as to create charge carriers by impact ionisation in the second portion.

Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets Nw, width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw, thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw, corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowire