Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.

Abstract: The present invention refers to an RF-transceiver and to a communication system. The invention is also related to a method for transmitting and processing control packets, particularly control packets transmitted by a baseband device to an RF-transceiver.

Abstract: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e.

Abstract: An interface apparatus is provided having a first register device and a second register device, which is connected in parallel with it. The register devices are configured to receive a data word. The interface apparatus includes a synchronization circuit, to which a first and a second clock signal is supplied and which is configured to emit a selection signal, which is derived from the first clock signal, for selection of the first or second register device for storage of a data word. The synchronization circuit is also configured to emit a control signal derived from the selection signal and the second clock signal, at a control output. The control output is coupled to a selection circuit, by means of which the output of one of the two register devices can be connected to the data output of the interface apparatus. Comparison of the selection signal with the second clock signal means that there is no need for an additional registration device.

Abstract: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e.

Abstract: An arrangement and a method for connecting a capacitor into a circuit and disconnecting it therefrom are disclosed. The capacitor includes two capacitor elements, each with a main terminal and an auxiliary terminal. The auxiliary terminals are connected to one another at a reference node to which a control signal can be coupled as a function of the desired capacitance value. The capacitance value is tapped at the main terminals of the capacitor elements. When the capacitor is switched on, a high quality level is obtained, and when the capacitor is switched off, low parasitic capacitance components are obtained. For this reason the described arrangement is particularly suitable for use in voltage-controlled oscillators.

Abstract: An arrangement and a method for connecting a capacitor into a circuit and disconnecting it therefrom are disclosed. The capacitor includes two capacitor elements, each with a main terminal and an auxiliary terminal. The auxiliary terminals are connected to one another at a reference node to which a control signal can be coupled as a function of the desired capacitance value. The capacitance value is tapped at the main terminals of the capacitor elements. When the capacitor is switched on, a high quality level is obtained, and when the capacitor is switched off, low parasitic capacitance components are obtained. For this reason the described arrangement is particularly suitable for use in voltage-controlled oscillators.