Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.

Abstract: A device includes a processor and memory. The memory has stored thereon a plurality of executable instructions. The executable instructions, when executed by the processor, cause the processor to: receive an access request affecting an operation of the device; facilitate encryption and/or authentication across an interface coupled to the device, wherein the interface is configured to secure the access request; and execute the access request.

Abstract: There is disclosed a method of processing an input set of indices that may contain one or more primitive restarts to determine which indices correspond to complete primitives. A modified version of the set of indices can then be written out that contains complete primitives. In particular this is done by determining, for each index in the set of indices, the index position of the start of a sequence of indices for a sequence of primitives that the index is part of, and then determined from this whether or not the index position corresponds to the start of a complete primitive.

Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: A method of operating a graphics processor that is configured to execute a graphics processing pipeline is provided. The method comprises the graphics processor reading, from an index buffer in external memory, a block of data comprising plural sets of indices, each set of indices comprising a sequence of indices indexing a set of vertices that defines a primitive of a plurality of primitives to be processed by the graphics processing pipeline. The graphics processor compresses the block of data to form a compressed version of the block of data, and stores the compressed version of the block of data in an internal memory of the graphics processor.

Abstract: When sampling a pair of mipmaps when performing anisotropic filtering when sampling a texture to provide an output sampled texture value for use when rendering an output in a graphics processing system, more positions along an anisotropy direction are sampled in the more detailed mipmap level than in the less detailed mipmap level. Each position that is sampled may have a single sample taken for it, or may be supersampled.

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

Abstract: A graphics processing pipeline (30) includes a programmable fragment shader (40) that is operable to, in response to a “test” instruction included in a fragment shader program that it is executing, trigger, if appropriate, the performance of an alpha-to-coverage operation (41), a late stencil test (42), and a late depth test (43) for a fragment being processed, and to then return updated coverage information to the fragment shader (40). This allows alpha-to-coverage and late stencil and depth test operations to be triggered and performed during shader execution, rather than having to wait until shader execution has been completed before performing those operations.

Abstract: A texture mapping apparatus, e.g. of a graphics processing unit, comprises texture fetching circuitry operable to receive a set of weight values for a convolution operation and fetch from memory a set of input data values on which the convolution operation is to be performed. The texture mapping apparatus further comprises texture filtering circuitry operable to perform a convolution operation using the set of received weight values and the set of fetched input data values. The texture mapping apparatus can allow a graphics processing unit to perform a variety of convolution operations in an efficient manner.

Abstract: A graphics processing apparatus comprises fragment generating circuitry to generate graphics fragments corresponding to graphics primitives, thread processing circuitry to perform threads of processing corresponding to the fragments, and forward kill circuitry to trigger a forward kill operation to prevent further processing of a target thread of processing corresponding to an earlier graphics fragment when the forward kill operation is enabled for the target thread and the earlier graphics fragment is determined to be obscured by one or more later graphics fragments. The thread processing circuitry supports enabling of the forward kill operation for a thread including at least one forward kill blocking instruction having a property indicative that the forward kill operation should be disabled for the given thread, when the thread processing circuitry has not yet reached a portion of the thread including the at least one forward kill blocking instruction.

Abstract: When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.

Abstract: A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8×8 sub-regions which encompasses the entire scene area. There is then a group of four 4×4 sets of sub-regions, then a group of sixteen 2×2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.

Abstract: A programmable execution unit (42) of a graphics processor includes a functional unit (50) that is operable to execute instructions (51). The output of the functional unit (50) can both be written to a register file (46) and fed back directly as an input to the functional unit by means of a feedback circuit (52). Correspondingly, an instruction that is to be executed by the functional unit (50) can select as its inputs either the fed-back output (52) from the execution of the previous instruction, or inputs from the registers (46). A register access descriptor (54) between each instruction in a group of instructions (53) specifies the registers whose values will be available on the register ports that the functional unit will read when executing the instruction, and the register address where the result of the execution of the instruction will be written to. The programmable execution unit (42) executes group of instructions (53) that are to be executed atomically.

Abstract: A programmable execution unit of a graphics processor that executes program instructions to perform graphics shading operations can use at least two different register file mapping configurations for mapping registers to execution threads. When a shader program is to be executed, how the shader program will use the registers is considered and the register file mapping configuration to use for the shader program is then selected based on the assessment of the register use by the shader program. Appropriate state information is then set to cause the threads being executed by the programmable execution unit to use the registers according to the selected register file mapping configuration when executing the shader program.

Abstract: There is provided an apparatus and method for comparing wide data types. The apparatus comprises processing circuitry to perform a plurality of comparison operations in order to compare a first value and a second value, each of the first value and the second value having a length greater than N bits, and each comparison operation operating on a corresponding N bits of the first and second values. The plurality of comparison operations are chained to form a sequence such that each comparison operation is arranged to output an accumulated comparison result incorporating the comparison results of any previous comparison operations in the sequence, and such that for each comparison operation other than a final comparison operation in the sequence the accumulated comparison result is provided for use as an input by a next comparison operation in the sequence.

Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: In a graphics processing system, when using a graphics texture that is stored in memory as YUV texture data, the YUV texture data is stored in the texture cache from which it is to be read when generating a render output such that the data values for a chrominance data element and its associated set of one or more luminance data elements of the texture are stored together as a group in the cache. The group of data in the cache is tagged with an identifier for the data values of the chrominance data element and its associated set of one or more luminance data elements that is useable to identify the chrominance data element and its associated set of one or more luminance data elements in the cache, and that is indicative of a position in the YUV graphics texture.

Abstract: An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and in addition provides reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation.