Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: An interface device presents a generic serial input/output (I/O) port, whose function is programmable according to a stored sequence of instructions executed by a programmable state machine. The instructions cause the programmable state machine to define operation of the serial I/O port according to a standard or other predetermined set of serial I/O communication parameters.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: A hollow building element of a plastics material comprises an upper wall, a lower wall, a pair of opposite side walls interconnecting the lateral edges of the upper and lower walls, a joining member in the form of a cylindrical, slotted, downwardly open flange provided at the upper edges of each side wall, the lower end of a side wall being integrally connected to an anchoring element for anchoring the building element to a support and the lower end of the opposite side wall being integrally connected to a guide member adapted to engage the anchoring member of an adjacent building element so as to maintain the lower ends of two adjacent side walls in spaced relationship and so as to form a tight connection between such elements.