Patents by Inventor Jos Accapadi

Jos Accapadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050246461
    Abstract: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.
    Type: Application
    Filed: April 29, 2004
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jos Accapadi, Herman Dierks, Andrew Dunshea, Dirk Michel
  • Publication number: 20050235125
    Abstract: A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jos Accapadi, Andrew Dunshea, Li Li, Grover Neuman, Mysore Srinivas, David Hepkin
  • Publication number: 20050210472
    Abstract: A method, computer program product, and a data processing system for queuing threads among a plurality of processors in a multiple processor system having a plurality of multi-processor modules is provided. A first thread to be processed is received and is identified as part of an existing process. A search for an idle processor is performed. The search is restricted to processors of a first multi-processor module associated with the existing process.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 22, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jos Accapadi, Larry Brenner, Andrew Dunshea, Dirk Michel
  • Publication number: 20050198386
    Abstract: Methods, systems, and products are disclosed for user defined preferred DNS routing that include mapping for a user in a data communications application a domain name of a network host to a network address for a preferred DNS server, wherein the preferred DNS server has a network address for the domain name; receiving from the user a request for access to a resource accessible through the network host; and routing to the preferred DNS server a DNS request for the network address of the network host, the DNS request including the domain name of the network host. In typical embodiments, mapping a domain name to a network address for a preferred DNS server is carried out by storing, through the data communication application, the domain name in association with the network address for a preferred DNS server in a data structure in computer memory.
    Type: Application
    Filed: February 19, 2004
    Publication date: September 8, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jos Accapadi, Mathew Accapadi, William Britton, Andrew Dunshea, Dirk Michel
  • Publication number: 20050086660
    Abstract: A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as CPI, that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.
    Type: Application
    Filed: September 25, 2003
    Publication date: April 21, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jos Accapadi, Andrew Dunshea, Dirk Michel, Mysore Srinivas
  • Publication number: 20050081183
    Abstract: A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.
    Type: Application
    Filed: September 25, 2003
    Publication date: April 14, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jos Accapadi, Andrew Dunshea, Dirk Michel, Mysore Srinivas
  • Publication number: 20050022186
    Abstract: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.
    Type: Application
    Filed: July 24, 2003
    Publication date: January 27, 2005
    Applicant: International Business Machines Corporation
    Inventors: Jos Accapadi, Andrew Dunshea, Dirk Michel, James Van Fleet