Abstract: The present invention relates to an extract of Bertholletia excelsa seeds obtained from extracting an at least partly deoiled press residue of Bertholletia excelsa seeds and to a method for preparing such extract. Furthermore, the present invention refers to a cosmetic or pharmaceutic composition comprising such extract as active ingredient and to the use of the extract or the composition for skin care.

Abstract: A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol in the word corresponding to the word address. A shift operation is performed during an operation of reading or of writing.

Abstract: A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol in the word corresponding to the word address. A shift operation is performed during an operation of reading or of writing.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: A digital signal processor is designed to execute variable-sized instructions that may include up to N elementary instruction codes. The processor comprises a memory program comprising I individually addressable, parallel-connected memory banks in which the codes of a program are recorded in an interlaced fashion, and a circuit for reading the program memory arranged to read a code in each of the I memory banks during a cycle for reading an instruction. A cycle for reading an instruction in the program memory includes reading a sequence of codes that includes the instruction code or codes to be read and can also include codes, belonging to a following instruction, that are filtered before the instruction is applied to execution units. The program memory of the digital signal processor does not include any no-operation type codes.

Abstract: The present invention relates to a method and device for estimation of the motion of a macroblock of pixels of a current image with respect to a reference window taken in a preceding image, including, in a first step, determining the cumulated distortion of the pixels of the current macroblock for a null motion vector in the reference window; choosing, as the motion vector of the current macroblock, the null vector if the distortion is lower than or equal to a first threshold; and otherwise choosing, in a second step, a vector for which the current macroblock exhibits a minimum distortion with respect to a macroblock of the reference window.

Abstract: A multiple-user processing system exchanges data elements with a central memory by a request system managed by a management circuit. The system furthermore has available a buffer memory to regulate the flow of information from the central memory.

Abstract: A matrix computation processor comprises a control unit and a data memory, and a plurality of computation units. The plurality of computation units are controlled by the control unit by means of a control bus comprising: a first group of wires connected to the plurality of computation units conveying a common instruction to the plurality of computation units; and a plurality of second groups of at least one wire, each being connected respectively to one of the plurality of computation units, conveying an instruction complement specific to each computation unit of the plurality of computation units.

Abstract: The multiplier-adder in the Galois fields can have parameters applied to it, i.e. it is possible to choose the Galois field CG(2.sup.m) in which the polynomial operations are performed, with m at most equal to N, N being predetermined by the designer. The multiplier-adder is made up of a decoder (10) organized as N identical elementary cells receiving the generator polynomial G(m:0) and supplying the generator polynomial without its least significant bit G(m-1:0) and a polynomial marking the degree of the generator polynomial, DG(m-1:0), and a computing matrix (20) organized as N columns of identical elementary cells receiving the polynomials A, B and C of the Galois field CG(2.sup.m) and supplying a polynomial result P=(A*B).sub.modulo G +C. The multiplier-adder has usage for example as a digital signal processing processors for error detecting and correcting encoding and decoding using BCH or RS codes.