Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.

Abstract: In an embodiment, an integrated circuit die includes a semiconductor substrate, patterned metal layers compiled over the semiconductor substrate, and a tapered multipath inductor formed in the patterned metal layers. The tapered multipath inductor includes, in turn, an inductor input terminal, an inductor output terminal, and N number of parallel inductor tracks electrically coupled between the inductor input terminal and the inductor output terminal. The parallel inductor tracks wind or wrap around an inductor centerline to define a plurality of multipath inductor windings including an innermost winding and an outermost winding. The parallel inductor tracks further vary in track width when progressing from the outermost winding to the innermost winding of the plurality of multipath inductor windings.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: A temperature sensor and method of temperature sensing is described. A first reference current is provided to a dual-slope ADC during a first slope time duration of a dual-slope ADC conversion cycle. A second reference current is provided to the dual-slope ADC during a second slope time duration of the dual-slope ADC conversion cycle. A digital codeword corresponding to a ratio of the first and second reference currents is then output by the dual-slope ADC. The first and second reference current ratio is related to the temperature.

Abstract: Various embodiments relate to a free running oscillator, that includes a switch capacitor based frequency-to-voltage converter (F2V), a comparator, and a voltage controlled oscillator (VCO), which may be collectively configured to reduce amplifier offset and flicker noise while increasing effective gain of the amplifier of the comparator. The F2V may produce a feedback voltage Vfb corresponding to frequencies of output of the VCO. The comparator may be configured to sample a reference voltage Vref using a sampling capacitor, compare Vref to Vfb, and generate an output based on any difference between Vref and Vfb, where the output may be integrated using an integrating capacitor of the comparator. The comparator may compensate for parasitic capacitance at the output of the amplifier by using an amplifier having two outputs, with the sampling capacitor and integrating capacitor being coupled to respectively different outputs of the amplifier.

Abstract: Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, fir

Abstract: A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal.

Abstract: A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal.

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Abstract: A frequency reference generator includes (i) an integrated frequency source having drive circuitry that drives a resonant (e.g., non-trimmable LC) tank to generate an oscillator signal, (ii) at least one temperature sensor that generates at least one measured temperature signal, and (iii) a frequency-adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a (e.g., sample-specific) mapping from temperature to a corresponding frequency-adjustment parameter (e.g., a divisor value for a fractional frequency divider). In some embodiments, a Colpitts oscillator generates the oscillator signal based on the measured temperature signal, where the Colpitts oscillator has voltage/temperature-compensation circuitry that compensates for variations in power supply voltage and operating temperature. Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T-trim or even no trim at all.

Abstract: An LC oscillator has a tank driver connected to cause a matched-resistance LC tank to oscillate. The LC tank has an inductor leg in parallel with a capacitor leg. The inductor leg has an explicit inductor having an implicit resistance level RL. The capacitor leg has an explicit capacitor having an implicit resistance level RC connected in series with an explicit resistor having an explicit resistance level RR, where RM=(RC+RR) is substantially equal to RL. The LC oscillator may have a non-trimmable LC tank and be part of a temperature-compensated frequency reference generator having standalone frequency adjustment circuitry that offers better than ±0.1% frequency accuracy (after single trim and batch calibration) over process, voltage, and temperature variations, and lifetime, which can serve as a low-cost replacement for a crystal oscillator for many applications.

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output.

Abstract: An oscillator system for an integrated circuit includes a first oscillator circuit, a second oscillator circuit, and calibration system. During a sampling routine, the calibration system is used to determine a sampled value based on a comparison of the output of the second oscillator and an external clock signal. The sampled value is stored in a memory. During a calibration routine, the calibration system determines a comparison value based on a comparison of the output of the second oscillator circuit and the output of the first oscillator circuit. The calibration circuit compares the comparison value with the sampled value to generate a tuning value to tune the frequency of the first oscillator circuit.

Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

Abstract: A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.

Abstract: An apparatus includes an antenna that is configured to transmit a radio frequency signal across a transmission media having a channel response impairment. A transmission path includes an encoder circuit that encodes data on a carrier signal; and a pre-equalizer circuit that is configured to pre-distort the encoded data according to equalizer coefficients representing the channel response impairment. A first equalization path includes circuitry that generates the equalizer coefficients based upon transients resulting from a presence change event for the carrier signal. A second equalization path includes circuitry that generates the equalizer coefficients based upon knowledge of encoded data on the carrier signal. Selection circuitry selects between the first equalization path and the second equalization path.

Abstract: An apparatus includes an antenna that is configured to transmit a radio frequency signal across a transmission media having a channel response impairment. A transmission path includes an encoder circuit that encodes data on a carrier signal; and a pre-equalizer circuit that is configured to pre-distort the encoded data according to equalizer coefficients representing the channel response impairment. A first equalization path includes circuitry that generates the equalizer coefficients based upon transients resulting from a presence change event for the carrier signal. A second equalization path includes circuitry that generates the equalizer coefficients based upon knowledge of encoded data on the carrier signal. Selection circuitry selects between the first equalization path and the second equalization path.