Patents by Inventor Jose A. Camarena
Jose A. Camarena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9909934Abstract: A determination is made if a temperature of a system has exceeded a hot threshold or a cold threshold. At room temperature, a first adjustment is determined for first nominal settings. The first nominal settings are for a first input to a first comparator. At room temperature, a second adjustment is determined for second nominal settings. The second nominal settings are for a first input to a second comparator. The temperature is monitored, during normal operation of the system, using a temperature dependent voltage with the first comparator adjusted with the first adjustment and second comparator adjusted with the second adjustment.Type: GrantFiled: February 28, 2014Date of Patent: March 6, 2018Assignee: NXP USA, Inc.Inventors: Jose A. Camarena, Khoi B. Mai, Dale J. McQuirk
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Patent number: 9703303Abstract: A voltage regulation system includes a voltage regulator configured to output a control signal indicating whether a voltage based on output of the voltage regulator is lower than a specified value. A charge pump is configured to output a voltage and a charging current. A pump monitor is configured to receive the control signal and the output voltage of the charge pump, and activate the charge pump when the control signal indicates the voltage based on output of the voltage regulator is lower than a specified value and the output voltage of the charge pump is lower than a threshold value.Type: GrantFiled: April 25, 2014Date of Patent: July 11, 2017Assignee: NXP USA, Inc.Inventors: Miten H. Nagda, Jose A. Camarena, Dale J. McQuirk
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Publication number: 20150309518Abstract: A voltage regulation system includes a voltage regulator configured to output a control signal indicating whether a voltage based on output of the voltage regulator is lower than a specified value. A charge pump is configured to output a voltage and a charging current. A pump monitor is configured to receive the control signal and the output voltage of the charge pump, and activate the charge pump when the control signal indicates the voltage based on output of the voltage regulator is lower than a specified value and the output voltage of the charge pump is lower than a threshold value.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Inventors: MITEN H. NAGDA, JOSE A. CAMARENA, DALE J. MCQUIRK
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Publication number: 20150247764Abstract: A determination is made if a temperature of a system has exceeded a hot threshold or a cold threshold. At room temperature, a first adjustment is determined for first nominal settings. The first nominal settings are for a first input to a first comparator. At room temperature, a second adjustment is determined for second nominal settings. The second nominal settings are for a first input to a second comparator. The temperature is monitored, during normal operation of the system, using a temperature dependent voltage with the first comparator adjusted with the first adjustment and second comparator adjusted with the second adjustment.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Inventors: JOSE A. CAMARENA, Khoi B. Mai, Dale J. McQuirk
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Patent number: 8638135Abstract: An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.Type: GrantFiled: October 13, 2011Date of Patent: January 28, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jose A. Camarena, Dale J. McQuirk, Miten H. Nagda
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Publication number: 20130093486Abstract: An integrated circuit includes first and second transistors, a switch, and a power-on reset (POR) circuit. The first transistor has a first current electrode, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode, and a control electrode. The switch is for coupling the first and second transistors to receive a power supply voltage in response to an asserted bias control signal. The POR circuit has a latch-up detection circuit coupled to receive the power supply voltage and to a control terminal of the switch. The latch-up detection circuit is for detecting a low voltage condition of the power supply voltage, and in response, deasserting the bias control signal to decouple the first and second transistors from the power supply voltage.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Inventors: JOSE A. CAMARENA, DALE J. MCQUIRK, MITEN H. NAGDA
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Patent number: 8228109Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.Type: GrantFiled: June 28, 2010Date of Patent: July 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Jose A. Camarena, Wenzhong Zhang
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Publication number: 20110316610Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.Type: ApplicationFiled: June 28, 2010Publication date: December 29, 2011Inventors: Michael A. Stockinger, Jose A. Camarena, Wenzhong Zhang
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Publication number: 20060284714Abstract: An electrical energy saving device or a magnetic induction device is adapted to surround a power delivery line. The magnetic induction device applies a magnetic field region to the power delivery line to reduce amperage up to about 25%. The magnetic induction device can be a one-piece or two-piece construction formed from a molded mixture. The mixture can include from about 35 wt % to about 45 wt % of an epoxy resin; from about 30 wt % to about 40 wt % of a polymer; from about 1 wt % to about 4 wt % of dimethyl sulfoxide; from about 4 wt % to about 7 wt % of a transition metal; from about 10 wt % to about 20 wt % of a magnetic material; and from about 1 wt % to about 5 wt % of a catalyst.Type: ApplicationFiled: July 12, 2005Publication date: December 21, 2006Inventor: Jose Camarena Villasenor
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Publication number: 20060283006Abstract: Method for manufacturing magnetic induction devices to control electricity entail mixing a resin with a polymer forming a mixture; adding a transition metal to the mixture forming a metalized mixture; adding dimethyl sulfoxide to the metalized mixture; mixture forming a liquid metalized mixture; adding a magnetic powder to the liquid metalized mixture forming a magnetized mixture; and adding a catalyst to the magnetized mixture forming a hot mixture due to an exothermic reaction. The hot liquid is poured into two or more molds. A gap or channel is formed in each section. The sections are allowed to cool, removed from the molds, and fastened together such that the channel runs the length of the device. A one-piece magnetic induction device can also be formed using these methods. The formed magnetic induction device applies a magnetic field region to a power delivery line to reduce amperage up to about 25%.Type: ApplicationFiled: July 12, 2005Publication date: December 21, 2006Inventor: Jose Camarena Villasenor
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Publication number: 20060284715Abstract: An electrical energy saving device or a magnetic induction device is adapted to surround a power delivery line. The magnetic induction device applies a magnetic field region to the power delivery line to reduce amperage up to about 25%. The magnetic induction device can be a one-piece or two-piece construction formed from a molded mixture. The mixture can include from about 35 wt % to about 45 wt % of an epoxy resin; from about 30 wt % to about 40 wt % of a polymer; from about 1 wt % to about 4 wt % of dimethyl sulfoxide; from about 4 wt % to about 7 wt % of a transition metal; from about 10 wt % to about 20 wt % of a magnetic material; and from about 1 wt % to about 5 wt % of a catalyst.Type: ApplicationFiled: July 12, 2005Publication date: December 21, 2006Inventor: Jose Camarena Villasenor
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Patent number: 6327126Abstract: A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately ½ of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.Type: GrantFiled: January 28, 2000Date of Patent: December 4, 2001Assignee: Motorola, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Geoffrey B. Hall, Jose A. Camarena, Joseph Chan, Fujio Takeda