Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another embodiment, the trench is filled with gettering material 72 such as polysilicon. The two gettering mechanisms may be combined 82,84. The invention is useful for providing gettering in bonded wafers and in silicon-on-insulator devices (FIGS. 4,5).

Abstract: A process including forming peaks and valleys in a bonding surface of a first wafer so that the peaks are at the scribe lines which define dice. The peaks and not the valleys of the first wafer is bonded to a bonding surface of a second wafer. The device forming steps are performed on one of the wafers. Finally, the wafer in which the devices are formed is cut through at the peaks to form the dice. The peaks may be substantially the size of the kerf produced by the cutting such that the dice are separated from the other wafer by the cutting step. Alternately, the peaks may have a width greater than the kerf produced by the cutting and remain attached to the other wafer by the remaining peak portions. The dice are then separated from the other wafer at the remaining peak portions by an additional step.

Abstract: A method including forming an alignment moat of a first depth on a first surface of a substrate and performing all backside processing, forming a first oxide layer on the first surface and oxide bonding it to a handling wafer by oxide bonding. The substrate is then thinned from a second surface opposite the first surface down to a thickness less than the depth of the alignment moat so the alignment moat is exposed at a third surface for front side processing.

Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.