Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Abstract: An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Abstract: An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method my further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Abstract: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Abstract: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Abstract: An automated process for designing a memory having row/column replacement is provided. In one embodiment, a potential solution array (50) is used in conjunction with the row/column locations of memory cell failures to determine values stored in the actual solution storage circuitry (92). A selected one of these vectors stored in the actual solution storage circuitry (92) is then used to determine rows and columns in memory array (20) to be replaced with redundant rows (22, 24) and redundant columns (26).

Abstract: A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

Abstract: Data processing units (14) within an integrated circuit (10) are connected by a common bus (16). Each data processing unit follows a predetermined protocol for communicating to other data processing units via the common bus (16). Further, predetermined control and/or data processing signals within the common bus (16) are multi-tasked (i.e. function multiplexed) for a normal and special modes of operation. A state machine (21) within each data processing unit (12) controls a clock circuit (23). The state machine (21) has a predetermined state diagram for controlling clock signals associated with the predetermined modes of operation.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a resistor digital to analog converter (32). In one form, the analog to digital converter uses a small amount of resistor test logic (44) to test for defects in the resistor array (42), the switch array (38), and the optional decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry, which includes some analog circuitry, is tested by using a pull-up function and a pull-down function that can be overdriven by properly functioning circuitry. As a result of using resistor test logic (44), a very quick pass/fail functional test using digital logic levels as inputs can be performed on the analog to digital converter (14). The quick functional test does not require analog inputs or time-consuming analog to digital conversions.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a capacitor digital to analog converter (30). In one form, the analog to digital converter uses a small amount of capacitor test logic (44) to test for opens and shorts in the capacitor array (42), the switch logic (38), and the decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by using AND and OR logical functions. As a result of using capacitor test logic (44), a very quick pass/fail functional test can be performed on the analog to digital converter (14) without requiring the analog to digital converter (14) to perform time-consuming analog to digital conversions.

Abstract: Transistors in a transistor array constructed in a testable multiple channel decoder are tested by setting the array in a test mode. A stuck low test, which detects an open circuit between a source and drain of a transistor, is executed by providing all address lines a first predetermined logic value. A stuck high test, which detects a short between a source and drain of a transistor, is executed by providing a first address line tested a second predetermined logic value and a second logic address line tested the first logic value.