Abstract: An ergometric treadmill for sport training comprising a screen, a control system and a system configured for collecting, processing, analyzing and visualizing the biomechanical response of a sportsperson while running on the ergometric treadmill; wherein the ergometric treadmill comprises (a) a plurality of MEMS sensors attached by means of supports to the ergometric treadmill connected to a data capture unit; and (b) a data processing unit configured to generate a plurality of parameters related to the physical exercise performed on the ergometric treadmill by a user and synthesize and show, in graphic form, the parameters generated for the user's biofeedback from the treadmill.

Abstract: The invention relates to a maritime structure for laying the foundations of buildings, installations or wind turbines by means of gravity in a marine environment, which has significant advantages for constructing, transporting, positioning and operating same, owing to the novel features introduced into the design thereof in comparison with existing types. The structure comprises a base in the shape of a chamfered equilateral triangle, having a sufficient height to optimise navigability, the base being formed by a frame of vertical walls that form hexagonal or triangular cells closed at the ends by a lower slab and an upper slab, and three closed towers having a regular hexagonal or circular cross section which are located in the corners of the base. The structure can be towed, completely installed, with a wind turbine or superstructure that same supports, and has low initial draft, high naval stability and low resistance to movement.

Abstract: The invention relates to a maritime structure for laying the foundations of buildings, installations or wind turbines by means of gravity in a marine environment, which has significant advantages for constructing, transporting, positioning and operating same, owing to the novel features introduced into the design thereof in comparison with existing types. The structure comprises a base in the shape of a chamfered equilateral triangle, having a sufficient height to optimise navigability, the base being formed by a frame of vertical walls that form hexagonal or triangular cells closed at the ends by a lower slab and an upper slab, and three closed towers having a regular hexagonal or circular cross section which are located in the corners of the base. The structure can be towed, completely installed, with a wind turbine or superstructure that same supports, and has low initial draft, high naval stability and low resistance to movement.

Abstract: A radio frequency identification (RFID) tag and a method of monitoring Quality of Service (QoS) of a RFID tag The RFID tag (200) comprising: a first communication module (201) to receive signals from a RFID reader (100) and including means for extracting energy from the received signals providing a supply voltage Vdd to the RFID tag (200); an energy storage module (203) to store said extracted energy from the received signals of the RFID reader (100); a second communication module (202) to communicate with an external device (300); a power output (204) to provide a power-supply voltage to the external device (300) using said stored energy; a control module (205) to perform a tracking of said power-supply voltage provided by said power output (204), wherein the first communication module (201) also transmits to the RFID reader (100) a quality indicator of an energy status of the RFID tag (200) based on the result of said tracking.

Abstract: A radio frequency identification (RFID) tag and a method of monitoring Quality of Service (QoS) of a RFID tag The RFID tag (200) comprising: a first communication module (201) to receive signals from a RFID reader (100) and including means for extracting energy from the received signals providing a supply voltage Vdd to the RFID tag (200); an energy storage module (203) to store said extracted energy from the received signals of the RFID reader (100); a second communication module (202) to communicate with an external device (300); a power output (204) to provide a power-supply voltage to the external device (300) using said stored energy; a control module (205) to perform a tracking of said power-supply voltage provided by said power output (204), wherein the first communication module (201) also transmits to the RFID reader (100) a quality indicator of an energy status of the RFID tag (200) based on the result of said tracking.

Abstract: The RFID tag comprising: a first communication module (201) for extracting energy from received signals from a RFID reader providing a supply voltage VDD to the RFID tag (200); an energy storage module (203) to store said extracted energy from the received signals; a first voltage limiter (205) adapted and configured to limit, during a start-up state of the RFID tag (200), said supply voltage VDD; and a second voltage limiter (206), different to and synchronized with said first voltage limiter (205), said second voltage limiter (206) being adapted and configured to be enabled during a stationary state of the RFID tag (200) by switching from the first voltage limiter (205) to the second voltage limiter (206), the first voltage limiter (205) having a fast response time and the second voltage limiter (206) having high and accurate limitation voltage in powered operation.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: The present invention relates to human interferon gamma variants with improved thermostability, to a nucleic acid encoding said variants, to a pharmaceutical composition containing them, and to their use for the treatment of a viral infection and of cancer.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A toy doll for teaching time of day and time relationships for daily activities, including a hollow body housing a speaker and an associated memory, the memory including controls for storage of selected words for announcement by the speaker, a display unit attached to the exterior of the toy doll including individually selectable display figures, and operator control buttons attached to the exterior of the doll for activating the speaker and the display unit. Means are also included for activation of a time of day display and announcement on demand, and for activation of preset alarms and announcements on demand for review purposes and for education of the intended user.