Patents by Inventor Jose Caparas

Jose Caparas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT ENCAPSULATION SYSTEM WITH VENT
    Publication number: 20070262423
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio Dimaano, Erick Dahilig, Sheila Marie Alvarez, Robinson Quiazon, Jose Caparas
  • Integrated circuit package system with multiple molding
    Publication number: 20070170554
    Abstract: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.
    Type: Application
    Filed: January 23, 2006
    Publication date: July 26, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Zigmund Camacho, Jose Caparas, Arnel Trasporto, Jeffrey Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WIDE FLANGE LEADFRAME
    Publication number: 20070170570
    Abstract: An integrated circuit package system provides a known good die module by providing a leadframe, providing a first die, attaching the first die to the leadframe, and encapsulating at least the first die. A second die is attached to the known good die module such that the known good die module is a substrate for the second die. The second die is electrically attached to the known good die module. At least the second die is additionally encapsulated.
    Type: Application
    Filed: January 24, 2006
    Publication date: July 26, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Camacho, Jose Caparas, Arnel Trasporto, Jeffrey Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWNSET LEAD
    Publication number: 20070108624
    Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.
    Type: Application
    Filed: May 4, 2006
    Publication date: May 17, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Jeffrey Punzalan, Sheila Alvarez, Jose Caparas, Robinson Quiazon
  • LARGE DIE PACKAGE STRUCTURES AND FABRICATION METHOD THEREFOR
    Publication number: 20070018290
    Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.
    Type: Application
    Filed: September 28, 2006
    Publication date: January 25, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Jeffrey Punzalan, Jose Caparas, Jae Hun Ku
  • DUAL ROW LEADFRAME AND FABRICATION METHOD
    Publication number: 20060186515
    Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.
    Type: Application
    Filed: April 21, 2006
    Publication date: August 24, 2006
    Applicant: STATS ChipPAC Ltd.
    Inventors: Jeffrey Punzalan, Jose Caparas, Jae Hun Ku
  • Dual row leadframe and fabrication method
    Publication number: 20050260787
    Abstract: A semiconductor package is provided. A leadframe including a die attach paddle, a number of inner leads, and a number of outer leads, and a number of extended lead tips on the number of outer leads. The inner edges of the number of extended lead tips are in substantial alignment with the inner edges of the number of inner leads. A die is attached to the die attach paddle. A number of bonding wires is used to connect the die to the number of inner leads and the extended lead tips on the number of outer leads, and an encapsulant is formed over the leadframe and the die.
    Type: Application
    Filed: May 13, 2004
    Publication date: November 24, 2005
    Applicant: ST ASSEMBLY TEST SERVICES
    Inventors: Jeffrey Punzalan, Jose Caparas, Jae Ku
  • Large die package structures and fabrication method therefor
    Publication number: 20050253230
    Abstract: A method for fabricating large die package structures is provided wherein at least portions of the leadtips of at least a plurality of leadfingers of a leadframe are electrically insulated. A die is positioned on the electrically insulated leadtips. The die is electrically connected to at least a plurality of the leadfingers.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 17, 2005
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Jeffrey Punzalan, Jose Caparas, Jae Ku