Abstract: A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: A system for real time bilinear interpolation includes a bilinear interpolation module capable of: generating pixel addresses for original image pixels of an original image needed for performing bilinear interpolation of the original image to form a resized image, wherein the generated pixel addresses assume all the original image pixels of the original image are accessible, and performing bilinear interpolation, and a pixel smart memory module capable: of sequentially receiving original image pixel rows of the original image an original image pixel row a time, predicting which original image pixel rows are needed for performing bilinear interpolation, storing only the needed sequentially received original image pixel rows in a memory, decoding the generated pixel addresses to form decoded addresses to access the needed original image pixel rows stored in the memory, and sending the needed original image pixel rows to the bilinear interpolation module for performing bilinear interpolation.

Abstract: A system configured to identify a target in a synthetic aperture radar signal includes: a feature extractor configured to extract a plurality of features from the synthetic aperture radar signal; an input spiking neural network configured to encode the features as a first plurality of spiking signals; a multi-layer recurrent neural network configured to compute a second plurality of spiking signals based on the first plurality of spiking signals; a readout neural layer configured to compute a signal identifier based on the second plurality of spiking signals; and an output configured to output the signal identifier, the signal identifier identifying the target.

Abstract: Described is a low power system for mobile devices that provides continuous, behavior-based security validation of mobile device applications using neuromorphic hardware. A mobile device comprises a neuromorphic hardware component that runs on the mobile device for continuously monitoring time series related to individual mobile device application behaviors, detecting and classifying pattern anomalies associated with a known malware threat in the time series related to individual mobile device application behaviors, and generating an alert related to the known malware threat. The mobile device identifies pattern anomalies in dependency relationships of mobile device inter-application and intra-applications communications, detects pattern anomalies associated with new malware threats, and isolates a mobile device application having a risk of malware above a predetermined threshold relative to a risk management policy.

Abstract: A system configured to identify a target in a synthetic aperture radar signal includes: a feature extractor configured to extract a plurality of features from the synthetic aperture radar signal; a spiking neural network configured to encode the features as a plurality of spiking signals; a readout neural layer configured to compute a signal identifier based on the spiking signals; and an output configured to output the signal identifier, the signal identifier identifying the target.

Abstract: Described is neuromorphic system for authorized user detection. The system includes a client device comprising a plurality of sensor types providing streaming sensor data and one or more processors. The one or more processors include an input processing component and an output processing component. A neuromorphic electronic component is embedded in or on the client device for continuously monitoring the streaming sensor data and generating out-spikes based on the streaming sensor data. Further, the output processing component classifies the streaming sensor data based on the out-spikes to detect an anomalous signal and classify the anomalous signal.

Abstract: A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Abstract: A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N?2; the circuit comprising: N input conductors; N programmable conductance circuits connected each between one of the input conductors and at least one output conductor; each programmable conductance circuit being arranged to be programmable at a value depending in a known manner from one of the first operands; each input conductor being arranged to receive from an input circuit an input train of voltage spikes having a spike rate that derives in a known manner from one of the second operands; and at least one output circuit arranged to generate an output train of voltage spikes having a spike rate that derives in a known manner from a sum over time of the spikes received on the at least one output conductor.

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Abstract: Described is neuromorphic system for authorized user detection. The system includes a client device comprising a plurality of sensor types providing streaming sensor data and one or more processors. The one or more processors include an input processing component and an output processing component. A neuromorphic electronic component is embedded in or on the client device for continuously monitoring the streaming sensor data and generating out-spikes based on the streaming sensor data. Further, the output processing component classifies the streaming sensor data based on the out-spikes to detect an anomalous signal and classify the anomalous signal.

Abstract: Described is a system for bounding box generation. The system operates on an image comprised of pixels having a one-bit value per pixel. Bounding boxes are generated around connected components in the image, the connected components having pixel coordinate and pixel count information. A ranking score is generated for each bounding box based on the pixel coordinate and pixel count information. The bounding boxes are filtered to remove bounding boxes that exceed a predetermined size and pixel count based on the pixel coordinate and pixel count information. The bounding boxes are further filtered to remove bounding boxes that fall below a predetermined ranking score, resulting in remaining bounding boxes. Finally, a device can be controlled or otherwise operated based on the remaining bounding boxes.

Abstract: Described is a low power system for mobile devices that provides continuous, behavior-based security validation of mobile device applications using neuromorphic hardware. A mobile device comprises a neuromorphic hardware component that runs on the mobile device for continuously monitoring time series related to individual mobile device application behaviors, detecting and classifying pattern anomalies associated with a known malware threat in the time series related to individual mobile device application behaviors, and generating an alert related to the known malware threat. The mobile device identifies pattern anomalies in dependency relationships of mobile device inter-application and intra-applications communications, detects pattern anomalies associated with new malware threats, and isolates a mobile device application having a risk of malware above a predetermined threshold relative to a risk management policy.

Abstract: A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

Abstract: A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L2 norm from the first degree of match, deriving a second squared L2 norm from the second degree of match, deriving a third squared L2 norm from the third degree of match, adding the second squared L2 norm and the third squared L2 norm, and subtracting the first squared L2 norm to form a sum, and dividing the sum by two.

Abstract: A method to perform convolutions between arbitrary vectors includes estimating a first degree of match for a difference between a first vector having a plurality of first elements and a second vector having a plurality of second elements using a first cluster of coupled oscillators, estimating a second degree of match for the first vector using a second cluster of coupled oscillators, estimating a third degree of match for the second vector using a third cluster of coupled oscillators, deriving a first squared L2 norm from the first degree of match, deriving a second squared L2 norm from the second degree of match, deriving a third squared L2 norm from the third degree of match, adding the second squared L2 norm and the third squared L2 norm, and subtracting the first squared L2 norm to form a sum, and dividing the sum by two.

Abstract: A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

Abstract: An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

Abstract: A liquid state machine pulse domain neural processor circuit comprising an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals.